Ac electrical characteristics, Cs2300-cp – Cirrus Logic CS2300-CP User Manual
Page 7
CS2300-CP
DS843F2
7
AC ELECTRICAL CHARACTERISTICS
Test Conditions (unless otherwise specified): VD = 3.1 V to 3.5 V; T
A
= -10°C to +70°C (Commercial Grade);
T
A
= -40°C to +85°C (Automotive Grade); C
L
= 15 pF.
Notes: 4.
t
CS
represents the time from the removal of CLK_IN by which CLK_IN must be re-applied to ensure that
PLL_OUT continues while the PLL re-acquires lock. This timeout is based on the internal VCO frequen-
cy, with the minimum timeout occurring at the maximum VCO frequency. Lower VCO frequencies will
result in larger values of t
CS
.
5.
Only valid in clock skipping mode; See
“CLK_IN Skipping Mode” on page 13
for more information.
6.
f
CLK_OUT
= 24.576 MHz; Sample size = 10,000 points; AuxOutSrc[1:0] = 11.
7.
In accordance with AES-12id-2006 section 3.4.2. Measurements are Time Interval Error taken with 3rd
order 100 Hz to 40 kHz bandpass filter.
8.
In accordance with AES-12id-2006 section 3.4.1. Measurements are Time Interval Error taken with 3rd
order 100 Hz Highpass filter.
9.
1 UI (unit interval) corresponds to t
CLK_IN
or 1/f
CLK_IN
.
Parameters
Symbol
Conditions
Min
Typ
Max
Units
Clock Input Frequency
f
CLK_IN
50 Hz
-
30
MHz
Clock Input Pulse Width
pw
CLK_IN
f
CLK_IN
< 175 kHz
f
CLK_IN
> 175 kHz
140
10
-
-
-
-
ns
ns
Clock Skipping Timeout
t
CS
(Notes
4
,
5
)
20
-
-
ms
Clock Skipping Input Frequency
f
CLK_SKIP
(
Note 5
)
50 Hz
-
80
kHz
PLL Clock Output Frequency
f
CLK_OUT
6
-
75
MHz
PLL Clock Output Duty Cycle
t
OD
Measured at VD/2
45
50
55
%
Clock Output Rise Time
t
OR
20% to 80% of VD
-
1.7
3.0
ns
Clock Output Fall Time
t
OF
80% to 20% of VD
-
1.7
3.0
ns
Period Jitter
t
JIT
(
Note 6
)
-
35
-
ps rms
Base Band Jitter (100 Hz to 40 kHz)
(Notes
6
,
7
)
-
50
-
ps rms
Wide Band JItter (100 Hz Corner)
(Notes
6
,
8
)
-
150
-
ps rms
PLL Lock Time - CLK_IN (
Note 9
)
t
LC
f
CLK_IN
< 200 kHz
f
CLK_IN
> 200 kHz
-
-
100
1
200
3
UI
ms