Cirrus Logic CDB5376 - Manual (Page 26)

CDB5376
26 DS612DB3
output sync, reset;
///////////////////////
// signal assignments
///////////////////////
assign sck = ssi_mc? 1'bz:sck_mc;
assign sdclk = drdy? 1'bz:sck_mc;
assign mosi = ssi_mc? 1'bz:mosi_mc;
assign ssi = ssi_mc? 1'bz:ssi_mc;
assign sdtki = sdtki_mc;
assign drdy_mc = drdy;
assign miso_mc = (drdy)? miso:sddat;
assign timeb = timeb_mc | timeb_pb | timeb_ext;
assign sync = sync_mc | sync_pb | sync_ext;
assign reset = reset_pb & reset_ext;
endmodule
cdb5376.v
///////////////////////////////////////////////////////////////////////////
// MODULE: CDB5376 top module
//
// FILE NAME: Top module for connecting CS5376 to C8051F320
// VERSION: 1.0
// DATE: Jan. 8, 2007
// COPYRIGHT: Cirrus Logic, Inc.
//
// CODE TYPE: Register Transfer Level
//
// DESCRIPTION: This module includes assignments for signals between
// the serial port of Bismarck and the SLAB micro.
//
///////////////////////////////////////////////////////////////////////////
module cdb5376 (
sck_mc,
mosi_mc,
ssi_mc,
sdtki_mc,
timeb_mc,
miso,
drdy,
sddat,
sync_mc,
sync_pb,
timeb_pb,
reset_pb,
reset_ext,
timeb_ext,
sync_ext,
miso_mc,
drdy_mc,
sck,
mosi,
ssi,
sdtki,
timeb,
sdclk,
sync,
reset
);
//////////////////
// input signals
//////////////////
input sck_mc, mosi_mc, ssi_mc;
input sdtki_mc, timeb_mc;
input miso,drdy,sddat;
input sync_mc, sync_pb, timeb_pb;
input reset_pb, reset_ext;
input timeb_ext, sync_ext;
//////////////////
//output signals
//////////////////
output miso_mc, drdy_mc;
output sck, mosi, ssi;
output sdtki,timeb,sdclk;
P 1
Figure 3. CPLD Default Signal Assignments