Cirrus Logic CDB5376 - Manual (Page 28)

CDB5376
28 DS612DB3
Pin # Pin Name Assignment Description
1 P0.1 SDTKI_MC Token to start CS5376A data transaction
2 P0.0 SYNC_IO SYNC signal from RS-485
3 GND Ground
4 D+ USB differential data transceiver
5 D- USB differential data transceiver
6 VDD +3.3 V power supply input
7 REGIN +5 V power supply input (unused on CDB5376)
8 VBUS USB voltage sense input
Pin # Pin Name Assignment Description
9 /RST
C2CK
RESETz Power on reset output, active low
Clock input for debug interface
10 P3.0
C2D
GPIO General purpose I/O
Data in/out for debug interface
11 P2.7 AIN- ADC input
12 P2.6 AIN+ ADC input
13 P2.5 CPLD3_MC General Purpose I/O
14 P2.4 CPLD2_MC General Purpose I/O
15 P2.3 CPLD1_MC General Purpose I/O
16 P2.2 CPLD0_MC General Purpose I/O
Pin # Pin Name Assignment Description
17 P2.1 TIMEB_MC Time Break signal to CS5376A
18 P2.0 SYNC_MC SYNC signal to CS5376A
19 P1.7 BYP_EN I2C bypass switch control
20 P1.6 SDA_DE I2C data driver enable
21 P1.5 SCL I2C clock in/out
22 P1.4 SDA I2C data in/out
23 P1.3 SSI_MCz SPI chip select output, active low
24 P1.2 MOSI_MC SPI master out / slave in
Pin # Pin Name Assignment Assignment
25 P1.1 MISO_MC SPI master in / slave out
26 P1.0 SCK1_MC SPI serial clock
27 P0.7 Internal VREF bypass capacitors
28 P0.6 SINT_MCz Serial acknowledge from CS5376A, active low
29 P0.5 RX UART receiver
30 P0.4 TX UART transmitter
31 P0.3 CLOCK_MC External clock input
32 P0.2 SDRDY_MCz Data ready acknowledge from CS5376A, active low