Cirrus Logic CS42L56 - Manual (Page 16)

16 DS851F2
CS42L56
Notes:
5. See Figure 4 .
6. SDOUT Code with HPFx=1 and HPFRZx=0.
7. See
“Parameter Definitions” on page 91 .
8. The full scale input voltage values given in the table refers to the maximum voltage difference between
the AINxx and AINxREF pins. Providing an input signal at these pins that exceeds the full scale input
voltage may result in clipping the analog input.
9. Measured between AINxx and AGND.
10. Providing a signal level higher than 300 mVpp on the AINxREF pin may degrade the PGA linearity and
adversely affect analog input performance. See Figure 5 .
Full-scale Signal Input Voltage (Note 8)
ADC
PGA=-1.5 dB, PREAMPx[1:0]=00
PGA=0 dB, PREAMPx[1:0]=00
PGA=+12 dB, PREAMPx[1:0]=00
PGA=0 dB, PREAMPx[1:0]=01
PGA=0 dB, PREAMPx[1:0]=10
PGA=+12 dB, PREAMPx[1:0]=01
PGA=+12 dB, PREAMPx[1:0]=10
0.76•VA
-
0.78•VA
-
-
-
-
-
0.80•VA
0.95•VA
0.82•VA
0.198•VA
0.259•VA
0.082•VA
0.064•VA
0.020•VA
0.84•VA
-
0.86•VA
-
-
-
-
-
0.76•VA
-
0.78•VA
-
-
-
-
-
0.80•VA
0.95•VA
0.82•VA
0.198•VA
0.259•VA
0.082•VA
0.064•VA
0.020•VA
0.84•VA
-
0.86•VA
-
-
-
-
-
Vpp
Vpp
Vpp
Vpp
Vpp
Vpp
Vpp
Vpp
AINxREF Input Voltage (Pseudo-Diff Mode) (Note 10) - - 0.300 - - 0.300 Vpp
Input Impedance (Note 9) ADC
PGA, PREAMPx[1:0]=00
PGA, PREAMPx[1:0]=01
PGA, PREAMPx[1:0]=10
-
-
-
- 60
40
12.65
4
-
-
-
- -
-
-
- 60
40
12.65
4
-
-
-
- k 
k 
k 
k 
DC Voltage at Analog Input (Pin Floating) - VA/2 - - VA/2 - V
ANALOG INPUT CHARACTERISTICS (CONTINUED)
Test Conditions (unless otherwise specified): Connections to the CS42L56 are shown in the “Typical Connection Diagrams” on
page 11 ; Input test signal is a 1 kHz sine wave through the passive input filter, PGA = 0 dB; All Supplies = VA;
GND = AGND = 0 V; T
A
= +25 C; Measurement bandwidth is 20 Hz to 20 kHz; Sample Frequency = 48 kHz. Measurement sig-
nal path is AINxx to SDOUT.
100 mV
PP
,
25 Hz
100 
1 F
AINxA
AINxREF
Figure 4. CMRR Test Configuration
1 µF
AINxx
AINxREF
1 µF
300 mV
PP,
1 kHz
100 
Figure 5. AINxREF Input Voltage Test Configuration