Cirrus Logic CS42L56 - Manual (Page 52)

52 DS851F2
CS42L56
13. Bring RESET low if the analog or digital supplies drop below the recommended operating condition
to prevent power glitch related issues.
4.12.2 Power-Down Sequence
1. To minimize pops on the headphone and/or line amplifier, each respective analog volume control
must first be muted and set to maximum attenuation. To reduce the volume transition delay while
minimizing pops, enable the analog zero cross function and disable the analog soft ramp function.
Register Controls: HPxMUTE, LINExMUTE, HPxVOL[6:0], LINExVOL[6:0], ANLGSFT, ANLGZC
2. The required wait time for muting the analog volume as described in 1 above depends on the worst
case zero cross timeout of 150 ms in passthrough mode. Wait at least 150 ms.
3. Disable soft ramp and zero cross volume transitions.
Register Controls: ANLGZC, DIGSFT
4. Set the PDN bit to ‘1’b.
5. Wait at least 100 µs.
The CODEC will be fully powered down after this 100 µs delay. Prior to the removal of the master
clock (MCLK), this delay of at least 100 µs must be implemented after step
4 to avoid premature
disruption of the CODEC’s power down sequence. A disruption in the CODEC’s power down
sequence may abruptly stop the charge pump, causing the headphone and/or line amplifiers to drive
the outputs up to the VCP supply. Such disruption may also cause clicks and pops on the output of
the DAC’s.
6. Optionally, MCLK may be removed at this time.
7. To achieve the lowest operating quiescent current, bring RESET low. All control port registers will be
reset to their default state.
8. Power Supply Removal (Option 1): Switch power supplies to a high impedance state. Note: VCP
must be removed prior to VA to maintain the relationship specified in “Recommended Operating
Conditions” on page 14 .
9. Power Supply Removal (Option 2): To minimize pops when the power supplies are pulled to ground,
a discharge resistor must be added in parallel with the capacitor on the FILT+ pin. With a 1 M 
resistor and a 2.2 µF capacitor on FILT+, FILT+ will ramp to ground in approximately 5 seconds.
After step 5 , wait the required time for FILT+ to ramp to ground before pulling VA to ground. Note:
VCP must be pulled to ground prior to VA to maintain the relationship specified in “Recommended
Operating Conditions” on page 14 .
Power Up Sequence Register Location
Step 5 , 10 ............................
Step 6 ..................................
Steps 7 ................................
Step 8 ..................................
Step 9 a, 12 a .........................
Step 9 b, 12 b .........................
“Power Down” on page 59
“Power Control 2 (Address 04h)” on page 59
“AIN Reference Configuration, ADC MUX (Address 1Ah)” on page 74
“Power Down DSP” on page 66
“Headphone Channel x Mute” on page 83
, “Line Channel x Mute” on page 84
“Headphone Volume Control” on page 84 , “Line Volume Control” on page 84
Power Down Sequence Register Location
Step 1 a................................
Step 1 b................................
Step 1 c................................
Step 3 ..................................
Step 4 ..................................
“Analog Soft Ramp” on page 64 , “Analog Zero Cross” on page 64
“Headphone Volume Control” on page 84 , “Line Volume Control” on page 84
“Headphone Channel x Mute” on page 83 , “Line Channel x Mute” on page 84
, “Analog Zero Cross” on page 64 , “Digital Soft Ramp” on page 64
“Power Down” on page 59