Cirrus Logic CS4396 - Manual (Page 11)

CS4396
DS288PP1 11
2.0 TYPICAL CONNECTION DIAGRAM
SCLK
Audio
Data
Processor
External Clock
MCLK
AGND
AOUTR+
CS4396
SDATA
VA
AOUTR-
+5V
Analog 0.1
µ
F + 1
µ
F
Mode
Select
M1
M0
AOUTL-
AOUTL+
DGND
VD
MUTE
Analog
Conditioning
Analog
Conditioning
7 22
24
23
19
20
18 9
1
15
13
11
12
4
14
5
M2
LRCK
1.0
µ
F +
RST
10
M3
M4
2
3
16
25
0.1 µf 10 µf
0.1 µf 10 µf
26
27
VREF
FILT+
FILT-
+5V
Analog
28
6 21
MUTEC
0.1 µf
8
17
+
+
CMOUT
C/H
Figure 4. Typical Connection Diagram - Hardware Mode (Control Port Mode)