Figure 20. format 0, left justified, Figure 21. format 1, i2s, Figure 22. format 2, right justified, 16-bit data – Cirrus Logic CS4396 User Manual
Page 25: Figure 23. format 3, right justified, 24-bit data, Format 1, i, Cs4396, Figure 21. format 1, i
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CS4396
DS288PP1
25
LRCK
SCLK
Left Channel
Right Channel
SDATA
+3 +2 +1 LSB
+5 +4
MSB -1 -2 -3 -4 -5
+3 +2 +1 LSB
+5 +4
MSB -1 -2 -3 -4
Figure 20. Format 0, Left Justified
LRCK
SCLK
Left Channel
Right Channel
SDATA
+3 +2 +1 LSB
+5 +4
MSB -1 -2 -3 -4 -5
+3 +2 +1 LSB
+5 +4
MSB -1 -2 -3 -4
Figure 21. Format 1, I
2
S
LRCK
SCLK
Left Channel
Right Channel
SDATA
6
5
4
3
2
1
0
9
8
7
15 14 13 12 11 10
6
5
4
3
2
1
0
9
8
7
15 14 13 12 11 10
32 clocks
Figure 22. Format 2, Right Justified, 16-Bit Data
LRCK
SCLK
Left Channel
SDATA
6
5
4
3
2
1
0
7
23 22 21 20 19 18
6
5
4
3
2
1
0
7
23 22 21 20 19 18
32 clocks
0
Right Channel
Figure 23. Format 3, Right Justified, 24-Bit Data
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