Cirrus Logic CS4953xx - Manual (Page 13)

CS4953xx Data Sheet
32-bit Audio Decoder DSP Family
DS705F2 13
5.9 Switching Characteristics — Internal Clock
Parameter Symbol Min Max Unit
Internal DCLK frequency
1
1. After initial power-on reset, F
dclk
= F
xtal
. After initial kick-start commands, the PLL is locked to max F
dclk
and remains
locked until the next power-on reset.
F
dclk
— 130 MHz
CS49530x-CVZ
CS49531x-CQZ
CS49531x-CVZ
CS49530x-DVZ
CS49531x-DVZ
— F
xtal
F
xtal
F
xtal
F
xtal
F
xtal
150
150
150
131
131 —
Internal DCLK period 1 DCLKP — 7.7 ns
CS49530x-CVZ
CS49531x-CQZ
CS49531x-CVZ
CS49530x-DVZ
CS49531x-DVZ
— 6.7
6.7
6.7
7.63
7.63
1/F
xtal
1/F
xtal
1/F
xtal
1/F
xtal
1/F
xtal
—