Cirrus Logic CS4953xx - Manual (Page 23)

CS4953xx Data Sheet
32-bit Audio Decoder DSP Family
DS705F2 23
5.16 Switching Characteristics — Digital Audio Slave Input Port
Note: In these diagrams, falling edge is the inactive edge of DAI_SCLK.
Figure 11. Digital Audio Input (DAI) Port Timing Diagram
Figure 12. DAI Slave Timing Diagram
Parameter Symbol Min Max Unit
DAI_SCLK period T
daiclkp
40 — ns
DAI_SCLK duty cycle — 45 55 %
DAI_LRCLK transition from DAI_SCLK active edge t
daisstlr
10 — ns
DAI_SCLK active edge from DAI_LRCLK transition t
daislrts
10 — ns
Setup time DAI_DATAn t
daidsu
10 — ns
Hold time DAI_DATAn t
daidh
5 — ns
D A I_S C LK
D A I_D A TA n
t
daidh
t
daidsu
DAI_SCLK
DAI_LRCLK
DAIn_DATAn
t
daislrts
T daiclkp
DAI_SCLK
DAI_LRCLK
t
daisstlr
T daiclkp
DAIn_DATAn