Cirrus Logic CS4953xx - Manual (Page 2)

CS4953xx Data Sheet
32-bit Audio Decoder DSP Family
DS705F2 2
Table of Contents
1 Documentation Strategy ............................................................................................................4
2 Overview .....................................................................................................................................4
2.1 Migrating from CS495xx(2) to CS4970x4 ................................................................................................. 5
2.2 Licensing .................................................................................................................................................. 5
3 Code Overlays ............................................................................................................................5
4 Hardware Functional Description ............................................................................................6
4.1 Coyote DSP Core ..................................................................................................................................... 6
4.1.1 DSP Memory ...............................................................................................................................6
4.1.2 DMA Controller ............................................................................................................................7
4.2 On-chip DSP Peripherals ......................................................................................................................... 7
4.2.1 Digital Audio Input Port (DAI) .......................................................................................................7
4.2.2 Digital Audio Output Port (DAO) ..................................................................................................7
4.2.3 Serial Control Port 1 & 2 (I
2
C or SPI) ..........................................................................................7
4.2.4 Parallel Control Port ....................................................................................................................7
4.2.5 External Memory Interface ..........................................................................................................7
4.2.6 General Purpose Input/Output (GPIO) ........................................................................................7
4.2.7 Phase-locked Loop (PLL)-based Clock Generator ......................................................................8
4.3 DSP I/O Description ................................................................................................................................. 8
4.3.1 Multiplexed Pins ..........................................................................................................................8
4.3.2 Termination Requirements ...........................................................................................................8
4.3.3 Pads ............................................................................................................................................8
4.4 Application Code Security ........................................................................................................................ 8
5 Characteristics and Specifications ..........................................................................................8
5.1 Absolute Maximum Ratings ...................................................................................................................... 8
5.2 Recommended Operating Conditions ...................................................................................................... 9
5.3 Digital DC Characteristics ........................................................................................................................ 9
5.4 Power Supply Characteristics .................................................................................................................. 9
5.5 Thermal Data (144-Pin LQFP) ............................................................................................................... 10
5.6 Thermal Data (128-pin LQFP) ................................................................................................................ 10
5.7 Switching Characteristics—
RESET ......................................................................................................... 11
5.8 Switching Characteristics — XTI ............................................................................................................ 11
5.9 Switching Characteristics — Internal Clock ............................................................................................ 12
5.10 Switching Characteristics — Serial Control Port - SPI Slave Mode ..................................................... 12
5.11 Switching Characteristics — Serial Control Port - SPI Master Mode ................................................... 13
5.12 Switching Characteristics — Serial Control Port - I
2
C Slave Mode ...................................................... 14
5.13 Switching Characteristics — Serial Control Port - I
2
C Master Mode .................................................... 15
5.14 Switching Characteristics — Parallel Control Port - Intel Slave Mode ................................................. 16
5.15 Switching Characteristics — Parallel Control Port - Motorola Slave Mode ......................................... 18
5.16 Switching Characteristics — Digital Audio Slave Input Port ................................................................. 20
5.17 Switching Characteristics — Digital Audio Output Port ........................................................................ 21
5.18 Switching Characteristics — SDRAM Interface .................................................................................... 22
6 Ordering Information ...............................................................................................................26
7 Environmental, Manufacturing, and Handling Information .................................................26
8 Device Pin-Out Diagram ..........................................................................................................27
8.1 128-Pin LQFP Pin-Out Diagram ............................................................................................................. 27
8.2 144-Pin LQFP Pin-Out Diagram ............................................................................................................ 28
9 Package Mechanical Drawings ...............................................................................................29