13 switching characteristics - uart, 13 switching characteristics — uart, Figure 7. uart timing – Cirrus Logic CS49DV8C User Manual
Page 18: Uart_clk uart_rxd uart_txd t, Uart_tx_en t
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Copyright 2008 Cirrus Logic, Inc.
DS868PP2
CS49DV8C Data Sheet
32-bit Audio DSP Family
5.13 Switching Characteristics — UART
Figure 7. UART Timing
Parameter
Symbol
Min
Max
Unit
UART_CLK period
1
1. The minimum clock period is limited to DCLKP/32 or the minimum value, whichever is larger.
t
uclki
266
-
ns
UART_CLK duty cycle
-
40
60
%
Setup time for UART_RXD
t
uckrxsu
5
-
Hold time for UART_RXD
t
uckrxdv
5
-
ns
Delay from CLK transition to TXD transition
t
ucktxdv
-
29
ns
UART_CLK
UART_RXD
UART_TXD
t
uckrxsu
t
ucktxdv
t
uckrxdv
UART_TX_EN
t
txen
t
txhz
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