Cirrus Logic CS5345 - Manual (Page 33)

DS658F4 33
CS5345
6.3 ADC Control - Address 04h
6.3.1 Functional Mode (Bits 7:6)
Function:
Selects the required range of sample rates.
6.3.2 Digital Interface Format (Bit 4)
Function:
The required relationship between LRCK, SCLK and SDOUT is defined by the Digital Interface Format
bit. The options are detailed in
Table 8 and may be seen in Figure 3 and Figure 4 .
6.3.3 Mute (Bit 2)
Function:
When this bit is set, the serial audio output of the both channels is muted.
6.3.4 High-Pass Filter Freeze (Bit 1)
Function:
When this bit is set, the internal high-pass filter is disabled. The current DC offset value will be frozen and
continue to be subtracted from the conversion result. See
“High-Pass Filter and DC Offset Calibration” on
page 24.
6.3.5 Master / Slave Mode (Bit 0)
Function:
This bit selects either master or slave operation for the serial audio port. Setting this bit selects Master
Mode, while clearing this bit selects Slave Mode.
7 6 5 4 3 2 1 0
FM1 FM0 Reserved DIF Reserved Mute HPFFreeze M/S
FM1 FM0 Mode
0 0 Single-Speed Mode: 4 to 50 kHz sample rates
0 1 Double-Speed Mode: 50 to 100 kHz sample rates
1 0 Quad-Speed Mode: 100 to 200 kHz sample rates
1 1 Reserved
Table 7. Functional Mode Selection
DIF Description Format Figure
0 Left-Justified, up to 24-bit data (default) 0 3
1 I²S, up to 24-bit data 1 4
Table 8. Digital Interface Formats