Cirrus Logic CS5351 - Manual (Page 19)

DS565F2 19
CS5351
4.6 Overflow Detection
The CS5351 includes overflow detection on both the left and right channels. This time multiplexed informa-
tion is presented as open drain, active low on pin 15, OVFL. The OVFL_L and OVFL_R data will go to a
logical low as soon as an overrange condition in either channel is detected. The data will remain low as
specified in the Switching Characteristics - Serial Audio Port section. This ensures sufficient time to detect
an overrange condition regardless of the speed mode. After the timeout, the OVFL_L and OVFL_R data will
return to a logical high if there has not been any other overrange condition detected. Please note that an
overrange condition on either channel will restart the timeout period for both channels.
4.6.1 OVFL Output Timing
In Left-Justified format, the OVFL pin is updated one SCLK period after an LRCK transition. In I²S format,
the OVFL pin is updated two SCLK periods after an LRCK transition. Refer to
Figures 23 and 24 . In both
cases the OVFL data can be easily demultiplexed by using the LRCK to latch the data. In left-justified for-
mat, the rising edge of LRCK would latch the right channel overflow status, and the falling edge of LRCK
would latch the left channel overflow status. In I²S format, the falling edge of LRCK would latch the right
channel overflow status and the rising edge of LRCK would latch the left channel overflow status.
4.7 Grounding and Power Supply Decoupling
As with any high-resolution converter, the CS5351 requires careful attention to power supply and grounding
arrangements if its potential performance is to be realized.
Figure 22 shows the recommended power ar-
rangements, with VA and VL connected to clean supplies. VD, which powers the digital filter, may be run
from the system logic supply or may be powered from the analog supply via a resistor. In this case, no ad-
ditional devices should be powered from VD. Decoupling capacitors should be as near to the ADC as pos-
sible, with the low value ceramic capacitor being the nearest. All signals, especially clocks, should be kept
away from the FILT+ and VQ pins in order to avoid unwanted coupling into the modulators. The FILT+ and
VQ decoupling capacitors, particularly the 0.01 µF, must be positioned to minimize the electrical path from
FILT+ and REFGND. The CDB5351 evaluation board demonstrates the optimum layout and power supply
arrangements. To minimize digital noise, connect the ADC digital outputs only to CMOS inputs.
4.8 Synchronization of Multiple Devices
In systems where multiple ADCs are required, care must be taken to achieve simultaneous sampling. To
ensure synchronous sampling, the MCLK and LRCK must be the same for all of the CS5351’s in the system.
If only one master clock source is needed, one solution is to place one CS5351 in Master Mode, and slave
all of the other CS5351’s to the one master. If multiple master clock sources are needed, a possible solution
would be to supply all clocks from the same external source and time the CS5351 reset with the inactive
edge of MCLK. This will ensure that all converters begin sampling on the same clock edge.