Cirrus Logic CS5364 - Manual (Page 18)

18 DS625F5
CS5364
SWITCHING SPECIFICATIONS - CONTROL PORT - SPI TIMING
Inputs: Logic 0 = DGND, Logic 1 = VLC, CDOUT C
L
= 30 pF
Notes:
1. Data must be held for sufficient time to bridge the transition time of CCLK.
2. For f
sck
<1 MHz
Figure 6. SPI Timing
Parameter Symbol Min Max Units
CCLK Clock Frequency f
sck
0 6.0 MHz
RST Rising Edge to CS Falling t
srs
20
-
ns
CS Falling to CCLK Edge t
css
20
CS High Time Between Transmissions t
csh
1.0 s
CCLK Low Time t
scl
66
ns
CCLK High Time t
sch
66
CDIN to CCLK Rising Setup Time t
dsu
40
CCLK Rising to DATA Hold Time (Note 1) t
dh
15
CCLK Falling to CDOUT Stable t
pd
-
50
Rise Time of CDOUT t
r1
25
Fall Time of CDOUT t
f1
Rise Time of CCLK and CDIN (Note 2) t
r2
100
Fall Time of CCLK and CDIN (Note 2) t
f2
CS
CCLK
CDIN
CDOUT
RST t
srs
t
scl
t
sch
t
css
t
r2
t
f2
t
csh
t
dsu
t
dh
t
pd