Cirrus Logic CS5364 - Manual (Page 27)

DS625F5 27
CS5364
4.8 Reset
The device should be held in reset until power is applied and all incoming clocks are stable and valid. Upon
de-assertion of RST, the state of the configuration pins is latched, the state machine begins, and the device
starts sending audio output data a maximum of 524288 MCLK cycles after the release of RST. When chang-
ing between mode configurations in Stand-Alone Mode, including clock dividers, serial audio interface for-
mat, master/slave, or speed modes, it is recommended to reset the device following the change by holding
the RST pin low for a minimum of one MCLK cycle and then restoring the pin to a logic-high condition.
4.8.1 Power-Down Mode
The CS5364 features a Power-Down Mode in which power is temporarily withheld from the modulators, the
crystal oscillator driver, the digital core, and the serial port. The user can access Power-Down Mode by
holding the device in reset and holding all clock lines at a static, valid logic level (either logic-high or logic-
low).
“DC Power” on page 11 shows the power-saving associated with Power-Down Mode.
4.9 Overflow Detection
4.9.1 Overflow in Stand-Alone Mode
The CS5364 includes overflow detection on all input channels. In Stand-Alone Mode, this information is
presented as open drain, active low on the OVFL pin. The pin will go to a logical low as soon as an over-
range condition in any channel is detected. The data will remain low, then time-out as specified in
Section
"Overflow Timeout" on page 14 . After the time-out, the OVFL pin will return to a logical high if there has not
been any other over-range condition detected. Note that an over-range condition on any channel will restart
the time-out period.
4.9.2 Overflow in Control Port Mode
In Control Port Mode, the Overflow Status Register interacts with the Overflow Mask Register to provide
interrupt capability for each individual channel. See
Section 5.4 "02h (OVFL) Overflow Status Register" on
page 33 for details on these two registers.