Cirrus Logic AN339 - Manual (Page 10)

AN339
AN339REV1
10 AN339REV1
8. CONCLUSION
The CS8416 offers many improvements and features beyond those of the CS8413/14. One of the CS8416’s primary
improvements is the reduction of baseband jitter on its recovered master clock.
As shown through experiment, this jitter reduction improves the THD+N performance of a converter sourced by the
CS8416 when compared to the same converter sourced by the CS8413/14. This demonstration supports the
CS8416 as a performance-enhanced replacement for existing CS8413/14 designs.
9. APPENDIX
9.1 Other Differences Between CS8413/14 and CS8416
Aside from those listed in Section 2 on page 1 , there are a number of other differences between the
CS8413/14 and the CS8416 that a designer considering a transition from the CS8413/14 to the CS8416
should be aware of. For reference, a list of some of the more significant differences is included below. For
complete details on any of these, please refer to each device’s datasheet.
9.2 System Set-Up
The data presented in this document is derived from measurements collected using one randomly selected
sample of each device. Measurements were taken at each device’s nominal voltage and at room tempera-
ture. Specifically, the CS8414 Revision A and the CS8416 Revision E were used.
To collect the audio performance data, the CS4398 high-performance DAC was chosen to demonstrate the
effect of each receiver’s output jitter. A single CDB4398 customer evaluation board was used to conduct
each test. The CS4398 FILT+ capacitor on the CDB4398 was increased from 100 µF to 1000 µF to ensure
a flat low-frequency THD+N response. The CS8414 located on the CDB4398 was used for all measure-
ments sourced by the CS8414, and a CDB8416 customer evaluation board was used to drive the CS4398
• The CS8416 is not pin compatible with the
CS8413/14.
• The CS8416 receiver input pins are not RS-422
compliant; the receiver input absolute maximum
voltage range is ±12 V for the CS8413/14 and
-0.3 V to VL + 0.3 V for the CS8416.
• The typical VA and VD supply voltages are 5 V
for the CS8413/14 and 3.3 V for the CS8416.
• The external PLL filter component values are dif-
ferent between the CS8416 and CS8413/14.
• The recovered clock frequency provided when
the PLL is unlocked is approximately 3 MHz for
the CS8413/14 and approximately 375 kHz or
750 kHz for the CS8416, depending upon the
selected RMCK ratio.
• The CS8416 recovered clock output pin is not
active during reset.
• There are various differences between the de-
vices’ C and U data framing implementations.
• The devices indicate their input sample rate dif-
ferently.
• Although typical I²S, Left-Justified, and Right-
Justified formats are supported by the devices,
there are various differences in other supported
serial audio output formats.
• The available controls over the state of the serial
data output during a receiver error condition are
different.
• There are various differences in the operation of
the devices’ error indication pins.
• Certain pins dedicated to the reporting of the C
data bits on the CS8414 are not available in the
CS8416’s hardware mode.
• The CS8413 is not directly register-compatible
with the CS8416 in software mode.
• The first five bytes of both channels’ C data are
register accessible in the CS8416’s software
mode, while the CS8413 allows sequential 1-
byte access to all 24-bits of a single channel’s C
data.
• There are various differences in the behavior of
the CS8413 and CS8416’s interrupt functions.