Cirrus Logic AN339 - Manual (Page 2)

AN339
AN339REV1
2 AN339REV1
Beyond those listed in the table, several other notable enhancements are available in the CS8416:
There are a number of other differences between the CS8413/14 and the CS8416 that a designer considering a tran-
sition from the CS8413/14 to the CS8416 should be aware of. For reference, a list of some of the more significant
differences is included in
Section 9.1 on page 10 .
3. BASICS OF CLOCK RECOVERY
The purpose of a S/PDIF receiver is to convert a 1-wire S/PDIF input signal containing both clock and data informa-
tion into discrete serial audio clock and data signals. A phase-locked loop (PLL) is used to derive a system clock
signal synchronous to the S/PDIF stream, and digital logic is used to decode the data.
In some limited applications, a S/PDIF receiver is used to source data into a purely digital system where clock jitter
needs to be only good enough to operate the internal digital components. However, the vast majority of systems with
a S/PDIF receiver also contain a D/A converter, an A/D converter, or a combination of the two, all being clocked by
the PLL recovered system clock generated by the S/PDIF receiver. In these systems, the jitter performance of the
S/PDIF recovered clock is of extreme importance because it has a direct impact on the system’s analog audio per-
formance.
As a result, an important qualifying factor for a
S/PDIF receiver is the performance of its recov-
ered clock. If the S/PDIF receiver does not pro-
vide a low-jitter recovered clock, then any
converters that use the clock for sampling can be
expected to exhibit reduced performance as a re-
sult.
The basic block diagram of the PLL is shown in
Figure 2 . The PLL uses a negative feedback loop
to compare the phase of the input clock to that of
the output clock. The resulting error voltage sig-
nal is low pass filtered and sent to an internal volt-
age-controlled oscillator (VCO). The VCO output
clock frequency is adjusted by the error signal voltage until the output clock frequency matches the input. The feed-
back loop contains a frequency divider so that the output clock frequency can be a multiple of the input frequency.
The amount of jitter present on the recovered clock is dependent on the characteristics of the PLL that generates
the clock. Since the CS8413/14 and CS8416 have different PLLs, the jitter on their recovered clocks is expected to
be different as discussed in the following section.
General Enhancements
• Optional automatic enable of de-emphasis filter
based on channel status bits.
• Dedicated S/PDIF receiver pass-through pin.
• Selectable recovered master clock frequency of
256 x Fs or 128 x Fs.
• SOIC, TSSOP, and QFN package options.
• Available in automotive grade.
Software Mode Enhancements
• Three configurable GPO pins.
• Data output muting capability.
• Data format detection and reporting.
• Channel status register update inhibit function.
• User data Q-channel subcode decoding into regis-
ters.
• IEC61937 Pc/Pd burst preamble registers.
Phase
Comparator
VCO
Recovered
Master Clock
Input
LPF
÷N
Figure 2. PLL Block Diagram