Cirrus Logic AN339 - Manual (Page 3)

AN339
AN339REV1
AN339REV1 3
4. CS8413/14 AND CS8416 CLOCK RECOVERY COMPARED
The primary difference between the CS8413/14 and CS8416 PLLs is found in the input source to each PLL’s phase
detector block. In each of these devices, digital logic analyzes the incoming biphase encoded S/PDIF stream to gen-
erate pulses that serve as the input to the phase comparator. The frequency of these pulses is referred to as the
phase detector update rate.
The more often the phase detector is updated, the more
often the VCO output frequency is corrected to match the
frequency of the input S/PDIF signal. A slower update
rate allows the VCO frequency a greater degree of wan-
der, leading to increased low frequency (audio-band) re-
covered clock jitter. See
Figure 3 and Figure 4 .
In practice, the CS8413/14 detector is updated once per
bit of the input S/PDIF signal; thus the update rate is data
dependent 64 times the input sample rate. With an up-
date rate of this frequency, the CS8413/14 has good au-
dio-band output jitter.
When the CS8416 was first released in 2002, its digital logic was designed to update its phase detector only once
per subframe of the S/PDIF input signal, or at 2 times the input sample rate. This was done as a measure designed
to support 192 kHz sample rates and to reduce data dependency. The unfortunate result of this slower update rate
was higher audio-band jitter present on the recovered master clock.
To address this issue and improve upon the CS8416 and
CS8413/14, in 2004 a new phase detector update rate
option was added to the CS8416.
When enabled, the newer update rate option causes the
phase detector to be updated on every edge of the bi-
phase S/PDIF input signal; thus the update rate is data
dependent from 64 to 128 times the input sample rate.
This new detector lowers the audio-band recovered clock
jitter and results in improved converter performance.
It’s important to note that the maximum sample rate is
limited to 108 kHz in this newer mode. The different de-
tector modes in the CS8416 are selected by the Phase Detector Update Rate (PDUR) control. PDUR set low (‘0’)
selects the original and slower update rate, while PDUR set high (‘1’) selects the new fast update rate. The PDUR
setting can be accessed at start-up through the TX pin in hardware mode, or in register 00h in software mode.
Since the CS8416 with PDUR = 1 has the same update rate or faster than the CS8413/14, the CS8416 is expected
to have lower audio-band recovered clock jitter.
Section 5 below details the results of jitter measurement tests that
empirically support this conclusion.
5. MEASURED JITTER COMPARISON
Although there are several different jitter specifications used to quantify the jitter present on a clock signal (period,
cycle-to-cycle, etc.), they are not all useful for correlating measured jitter to the THD+N performance of an audio
converter that uses the measured clock signal to drive its sampling circuits.
The best jitter specification for this correlation is ‘baseband jitter’ as defined in section 3.4.2 of AES-12id-2006. A
baseband jitter measurement band-passes the measured jitter signal, calculating the jitter amplitude over a frequen-
cy band from 100 Hz to 40 kHz. Jitter outside of this frequency band is said to have no effect on the THD+N perfor-
mance of an audio converter because the resulting modulation tones will either be psycho-acoustically masked (jitter
less than 100 Hz) or higher than the upper limit of the 20 kHz audio band (jitter greater than 40 kHz).
Time (seconds)
VCO
Frequency
(MHz)
Ideal VCO
Frequency
Phase Detector
Update Rate
VCO Jitter
Figure 3. Slow Phase Detector Update Rate
Time (seconds)
VCO
Frequency
(MHz)
Ideal VCO
Frequency
Phase Detector
Update Rate
VCO Jitter
Figure 4. Fast Phase Detector Update Rate