Achronix Speedster22i PCIe - Manual (Page 21)

UG030, April 26, 2013 21
completes. Writes perform reasonably well in either case since writes are
always posted and software will generally not block on write transactions.
In the Target with Master DMA design each of the three interfaces (external
SDRAM, internal SRAM, and DMA registers/General Purpose I/O) are
assigned a memory Base Address Register. The Target Control module steers
the incoming packets to the appropriate destination based upon the Base
Address Register that was hit and formats the data (if needed) to the
appropriate width.
As a target, the design receives Posted Request packets containing write
requests and data and performs the writes on the addressed interface. The
design receives Non-Posted Request packets containing read requests,
performs the read on the addresses interface, and then transmits one or more
Completion packets containing the requested read data.
The DMA Control module masters transactions on the PCI Express bus (it
generates requests, rather than just responding to requests). System software
controls the DMA transactions via target writes and reads to the Internal
Registers.
As a master, the design transmits Posted (write request + data) and Non-
Posted (read request) requests and monitors the RX bus for (reads only) the
corresponding Completion packets containing the transaction status/data.
Since the SDRAM Controller module must be shared, an SDRAM Arbiter is
required to arbitrate between servicing DMA and target SDRAM accesses.
Since there are two modules that need access to the Transmit and Receive
Interfaces, arbiters are required.
The Target with Master DMA design is well suited to applications that need
to move a lot of data at very high throughput rates. The higher throughput
comes at a price however. Design complexity is significantly greater than a
target-only design and system software is more complicated to write.
PCIe-Core
Arbiter
Arbiter
TX
RX
DMA
Control
Target
Control
Arbiter
Internal
Registers
SDRAM
Cntrl
Internal
SRAM
GPIO
SDRAM
Speedster22i
Figure 7: AXI Target with Master DMA (Control Flow)