Cypress CY7C1312BV18 User Manual
Mbit qdr™-ii sram 2-word burst architecture, Features, Configurations
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Table of contents
Document Outline
- Features
- Configurations
- Functional Description
- Selection Guide
- Logic Block Diagram (CY7C1310BV18)
- Logic Block Diagram (CY7C1910BV18)
- Logic Block Diagram (CY7C1312BV18)
- Logic Block Diagram (CY7C1314BV18)
- Pin Configuration
- Pin Definitions
- Functional Overview
- Application Example
- Truth Table
- Write Cycle Descriptions
- Write Cycle Descriptions
- Write Cycle Descriptions
- IEEE 1149.1 Serial Boundary Scan (JTAG)
- TAP Controller State Diagram
- TAP Controller Block Diagram
- TAP Electrical Characteristics
- TAP AC Switching Characteristics
- TAP Timing and Test Conditions
- Identification Register Definitions
- Scan Register Sizes
- Instruction Codes
- Boundary Scan Order
- Power Up Sequence in QDR-II SRAM
- Maximum Ratings
- Operating Range
- Electrical Characteristics
- Capacitance
- Thermal Resistance
- Switching Characteristics
- Switching Waveforms
- Ordering Information
- Package Diagram
- Document History Page
- Sales, Solutions, and Legal Information