Pin definitions – Cypress CY7C1462AV33 User Manual

Page 6

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CY7C1460AV33
CY7C1462AV33
CY7C1464AV33

Document #: 38-05353 Rev. *D

Page 6 of 27

CLK

Input-
Clock

Clock Input. Used to capture all synchronous inputs to the device. CLK is qualified with
CEN. CLK is only recognized if CEN is active LOW.

Input-

Synchronous

Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction
with CE

and CE

to select/deselect the device.

Input-

Synchronous

Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in
conjunction with CE

and CE

to select/deselect the device.

Input-

Synchronous

Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction
with CE

and

to select/deselect the device.

Input-

Asynchronous

Output Enable, active LOW. Combined with the synchronous logic block inside the device
to control the direction of the I/O pins. When LOW, the I/O pins are allowed to behave as
outputs. When deasserted HIGH, I/O pins are tri-stated, and act as input data pins. OE is
masked during the data portion of a write sequence, during the first clock when emerging
from a deselected state and when the device has been deselected.

CEN

Input-

Synchronous

Clock Enable Input, active LOW. When asserted LOW the clock signal is recognized by
the SRAM. When deasserted HIGH the clock signal is masked. Since deasserting CEN
does not deselect the device, CEN can be used to extend the previous cycle when required.

I/O-

Synchronous

Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that is
triggered by the rising edge of CLK. As outputs, they deliver the data contained in the
memory location specified by A

during the previous clock rise of the read cycle. The

direction of the pins is controlled by OE and the internal control logic. When OE is asserted
LOW, the pins can behave as outputs. When HIGH, DQ

–DQ

are placed in a tri-state

condition. The outputs are automatically tri-stated during the data portion of a write
sequence, during the first clock when emerging from a deselected state, and when the
device is deselected, regardless of the state of OE.

DQP

I/O-

Synchronous

Bidirectional Data Parity I/O lines. Functionally, these signals are identical to DQ

[31:0]

During write sequences, DQP

is controlled by BW

, DQP

is controlled by BW

, DQP

controlled by BW

, and DQP

is controlled by BW

, DQP

is controlled by BW

, DQP

controlled by BW

, DQP

is controlled by BW

, DQP

is controlled by BW

MODE

Input Strap Pin

Mode Input. Selects the burst order of the device. Tied HIGH selects the interleaved burst
order. Pulled LOW selects the linear burst order. MODE should not change states during
operation. When left floating MODE will default HIGH, to an interleaved burst order.

TDO

JTAG serial output

Synchronous

Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK.

TDI

JTAG serial input

Synchronous

Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK.

TMS

Test Mode Select

Synchronous

This pin controls the Test Access Port state machine. Sampled on the rising edge of
TCK.

TCK

JTAG-Clock

Clock input to the JTAG circuitry.

Power Supply

Power supply inputs to the core of the device.

DDQ

I/O Power Supply Power supply for the I/O circuitry.

Ground

Ground for the device. Should be connected to ground of the system.

N/A

No connects. This pin is not connected to the die.

NC/72M

N/A