Digilent 410-087P-KIT - Manual (Page 105)

Spartan-3E Starter Kit Board User Guide www.xilinx.com 105
UG230 (v1.0) March 9, 2006
DDR SDRAM Connections R
Da
ta
SD_DQ15 H5 Data input/output
SD_DQ14 H6
SD_DQ13 G5
SD_DQ12 G6
SD_DQ11 F2
SD_DQ10 F1
SD_DQ9 E1
SD_DQ8 E2
SD_DQ7 M6
SD_DQ6 M5
SD_DQ5 M4
SD_DQ4 M3
SD_DQ3 L4
SD_DQ2 L3
SD_DQ1 L1
SD_DQ0 L2
Co
nt
ro
l
SD_BA1 K6 Bank address inputs
SD_BA0 K5
SD_RAS C1 Command inputs
SD_CAS C2
SD_WE D1
SD_CK_N J4 Differential clock input
SD_CK_P J5
SD_CKE K3 Active-High clock enable input
SD_CS K4 Active-Low chip select input
SD_UDM J1 Data Mask. Upper and Lower data masks
SD_LDM J2
SD_UDQS G3 Data Strobe. Upper and Lower data strobes
SD_LDQS L6
SD_CK_FB B9 SDRAM clock feedback into top DCM
within FPGA. Used by some DDR SDRAM
controller cores
Table 13-1: FPGA-to-DDR SDRAM Connections (Continued)
Category
DDR SDRAM
Signal Name
FPGA Pin
Number Function