Digilent DDR-2 Opus Card - Manual (Page 10)

Opus Card – DDR-2 Interface
Reference Manual
12/03/2010 07:35 AM 10 Copyright © 2009-2010 by CML
2.3.4 Burst Memory Write - Eight 32-bit Words
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
Write
Addr
Wd 12 Wd 34
0x0
Word 1
Addr
Byte Enables (All 1's for a burst)
Idle Wait_WrReq Wr_Brst1 Wr_Brst2
Word 2 Word 3 Word 4
Addr+0x4 Addr+0x8 Addr+0xC
Idle Save_W1 Save_W2 Save_W3
Addr+0x1C Addr+0x18 Addr+0x14 Addr+0x10
Word 5 Word 6 Word 7 Word 8
Write
Addr+4
Wd 56 Wd 78
Save_W2 Save_W3 Wr_Brst1 Wr_Brst2
0x0
Wr_BrstD Save_W1 Wr_BrstD
TimeGen
DDR2_Clk
Bus2IP_Clk
Bus2IP_CS
Bus2IP_Burst
Bus2IP_RNW
Bus2IP_Addr
Bus2IP_BE
Bus2IP_WrReq
Bus2IP_Data
IP2Bus_AddrAck
IP2Bus_WrAck
App_AF_WREn
App_AF_Cmd
App_AF_Addr
App_WDF_WREn
App_WDF_Data
App_WDF_Mask_Data
State