Digilent DDR-2 Opus Card - Manual (Page 8)

Opus Card – DDR-2 Interface
Reference Manual
12/03/2010 07:35 AM 8 Copyright © 2009-2010 by CML
2.3.2 Non-burst, 64-bit Memory Write
The diagram below is for a non-burst memory write to a single 64-bit word. The Bus2IP_BE bus
is used to determine which bytes to write in the 64-bit word. The use of the Bus2IP_BE bus
enables the hardware controlling the PLB slave to also write eight, sixteen, or thirty-two bit
values to a 64-bit memory location.
1 2 3 4 5 6 7 8 9 10 11
Write
Address
Word1 Word2
Mask1 Mask2
64-bit Data
Address
Byte Enables
Idle Wait_WrReq Wr_Word1 Wr_Word2 Idle
TimeGen
DDR2_Clk
Bus2IP_Clk
Bus2IP_CS
Bus2IP_RNW
Bus2IP_Addr
Bus2IP_BE
Bus2IP_WrReq
Bus2IP_Data
IP2Bus_AddrAck
IP2Bus_WrAck
App_AF_WREn
App_AF_Cmd
App_AF_Addr
App_WDF_WREn
App_WDF_Data
App_WDF_Mask_Data
State