Digilent DDR-2 Opus Card - Manual (Page 15)

Opus Card – DDR-2 Interface
Reference Manual
12/03/2010 07:35 AM 15 Copyright © 2009-2010 by CML
3.2 Read FIFO State Machine
The Read FIFO state machine currently has four states to support the reading of data from the
read FIFO to the PLB slave. Transitions from one state to the next occur on the rising edge of
DDR2_Clk and the state machine is synchronously reset to Idle when Bus2IP_Reset is ‘1’. Each
state is described below:
State
Description
Idle Waiting for the read FIFO to contain data during a burst read. The state
machine transitions to the FIFO_Rd state once data is detected in the read FIFO.
FIFO_Rd For a 64-bit PLB slave, the state machine transitions to the Lo_Bits state when
Bus2IP_Clk is currently ‘1’. For a 32-bit PLB slave, the state machine
transitions to the Hi-Bits state when Bus2IP_Clk is currently ‘1’.
Hi_Bits This state is only used for a 32-bit PLB slave and will cause the high order bits
of the read FIFO to be placed on the IP2Bus_Data bus. The state machine
transitions to the Lo_Bits state when Bus2IP_Clk is currently ‘1’.
Lo_Bits This state will output the read FIFO data to the IP2Bus_Data bus. For a 64-bit
PLB slave, the read FIFO data is placed on the IP2Bus_Data bus. For a 32-bit
PLB slave, the low order bits of the read FIFO are placed on the IP2Bus_Data
bus. The state machine transitions to FIFO_Rd when there is data left to
transfer. Otherwise the state machine will transition to Idle when Bus2IP_Clk is
currently ‘1’.