ADLINK PXI-2022 - Manual (Page 32)

24 Function Block and Operation Theory
4.2 Basic AI Acquisition
In this section, the basic acquisition timing is explained.
4.2.1 Analog Input Path
The following figure shows the block diagram of the single analog
input path of a PXI-2020/2022. Each path provides a choice of 1G
Ω input impedance or high impedance. The gain amplifier is opti-
mized for ±10 V and ±2.5 V input range with low noise and high
dynamic range. An anti-aliasing filter is also adopted to eliminate
high frequency noise. The 16-bit ADC provides not only accurate
DC performance but also high signal-to-noise ratio, high spurious-
free dynamic range in AC performance.
Figure 4-2: PXI-2020/2022 Analog Input Path
4.2.2 Basic Acquisition Timing
The trigger is a signal that starts or stops the acquisition. In post-
trigger mode and delay trigger mode, the trigger is used to initiate
acquisition. In pre-trigger mode, the trigger is used to stop acquisi-
tion. In middle-trigger mode, the trigger is used to inform the acqui-
sition engine to acquire the specific number of data and then stop.
Timebase is a clock that sent to the ADC of each channel and the
acquisition engine for essential timing functionality. The source of
timebase can be either internal oscillator or external clock genera-
tor. Usually the maximum sampling rate of a Data Acquisition
Module is determined by the speed of timebase. However, other
sampling rate can be achieved by specifying a scan interval coun-
An ti -al iasi ng
Fil ter
Calibration S ource +
P rot ect ion
Ci rcuitry
Gain = 1 or 4
16-bit
250 KS ADC
Onboard
Me mo ry
P CI Interface Hi I mpedance
B uff er
Calibrat ion S ource -
AI+
A I-