ADLINK PCI-7256 - Manual (Page 35)

Operation Theorem • 27
4.3 Interrupt Architecture
PCI-7256 has a powerful dual interrupt routing scheme including change-of-
state detection and interrupt sources on digital input channel 0 and channel 1.
Using these interrupts well can make you handle more complicated
information from outside enviroment and release your computer from a heavy
burden in dealing with digital input data. Note that the dual interrupts do not
mean the card occupies two IRQ levels.
There are two interrupt modes in PCI-7256, but you can only choose one of
them at one time. Table3.2 shows all of the combinations of interrupt modes.
4.4 Change of State(COS) Interrupt
What is COS?
The COS (Change of State) means either the input state(logic level) changes
from low to high, or from high to low. The COS detection circuit will detect
the edge of level change. In the PCI-7256 card, the COS detection circuit is
applied to all the input channels. When any channel changes its logic level,
the COS detection circuit generates an interrupt request to PCI controller.
COS Detection
The following timing is an example of COS operation. All of the enabled DI
channels’ signal level change will be detected to generate the interrupt
request.
While the interrupt request generates, the corresponding DI data will also be
latched into the COS latch register. In our COS architecture, the DI data are
sampled by a 8.25MHz clock. It means the pulse width of the digital input
have to last longer than 122 ns, or the COS latch register won’t latch the
correct input data. The COS latch register will be erased after clearing the
interrupt request.
Digital Input
(16 CH are all enabled)
Interrupt
Request
0x321A 0xC76A 0xFFFF
COS Latch
Register
0x0000 0xC76A 0x0000 0xFFFF 0x0000
Clear IRQ Clear IRQ
Figure4.4 Timing of COS