ADLINK PXIS-3320 User Manual
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Table of contents
Document Outline
- Table of Contents
- List of Tables
- List of Figures
- 1 Introduction
- 2 Chassis Overview
- 3 Installation
- 4 Troubleshooting and Preventive Maintenance
- A Specifications
- B Backplane Drawing and Pin Assignments
- B.1 Backplane Layout
- B.2 Backplane CBX-6015 Connectors Pin Assignments
- B.3 Bus Segments and Interrupt Routings
- B.4 Bus Segments and Interrupt Routings
- B.5 Miscellaneous Connectors Pin Assignments
- CN1, CN7, CN8, CN9: ATX-like DC Power input connectors
- PCI VIO Selection Screw Terminals
- J6 INH#: DC power inhibit signal
- J8 RST#: System reset signal
- J9 FAL#: Power supply fail input
- J5: Connector for LED power status
- CN5: SMB (System Management Bus) connector
- JP1: 10 MHz Reference Clock
- J2: POWER SENSE
- Important Safety Instructions
- Warranty Policy