ADLINK HSL-DI16DO16-M-NN - Manual (Page 9)

List of Figures v
List of Figures
Figure 1-1: HSL topology ............................................................. 2
Figure 1-2: Traditional distributed PLC architecture .................... 5
Figure 1-3: Networking PLC......................................................... 6
Figure 1-4: HSL as distributed PLC ............................................. 7
Figure 1-5: Time-deterministic DAQ using HSL........................... 8
Figure 1-6: HSL technology brief -1 ........................................... 14
Figure 1-7: HSL technology brief-2 ............................................ 15
Figure 1-8: HSL I/O polling cycle ............................................... 17
Figure 1-9: Master-slave communication architecture ............... 18
Figure 1-10: Multiple master cards in one IPC............................. 20
Figure 1-11: HSL system layout example-serial wiring................ 21
Figure 1-12: HSL wiring – RS-422 with multi-drop....................... 23
Figure 1-13: HSL networking topology – Serial ........................... 24
Figure 2-1: PCI-7854 front view ................................................. 29
Figure 2-2: PCI-7853/7854 Layout............................................. 31
Figure 2-3: PMC-7852/G Layout................................................ 32
Figure 2-4: SW1 – Transmission Rate Setting........................... 34
Figure 2-5: Top View of PMC-7852/G, for JP 1, 2, 3, 4, 5, 6 jumper
settings. ................................................................... 34
Figure 2-6: Functional Block diagram of HSL master ................ 36
Figure 5-1: Type 1...................................................................... 92
Figure 5-2: Type 2...................................................................... 92
Figure 5-3: Type 3...................................................................... 93
Figure 6-1: Programming Flow ................................................ 109