ADLINK VPX6000 - Manual (Page 34)

22 Board Interfaces
4.3 VPX6000 VPX Connector Pin Assignments
P0 Connector Pin Assignment
Pin A B C D E F G
1 P12V P12V P12V NC P12V P12V P12V
2 P12V P12V P12V NC P12V P12V P12V
3 P5V P5V P5V NC P5V P5V P5V
4 NVMRO SYSTEM RESET GND NC GND I2C_DAT I2C_CLK
5 IPMC_DAT IPMC_CLK GND P3V3_AUX GND GA4 GAP
6 GA0 GA1 GND NC GND GA2 GA3
7 JTAG_TRST JTAG_TMS GND JTAG_TDI JTAG_TDO GND JTAG_TCK
8 GND NC NC GND REF_CLK+ REF_CLK- GND
Signal I/O Description
P12V I +12V power source
P5V I +5V power source
NVMRO I/O
Non-Volatile Memory Read Only
Derived by the system controller/plug in module
SYSTEM RESET I/O System Reset, generally input, sourced by the system controller
NC ? Not Connected
I2C_DAT I/O Node A PCH SMBus data
I2C_CLK I/O Node A PCH SMBus clock
IPMC_DAT I/O IPMC I2C bus data
IPMC_CLK I/O IPMC I2C bus clock
P3V3_AUX I 3.3V auxiliary power
GPA/GA[0..4] I Geographical Address Inputs 0-4, Parity
JTAG_***** I/O JTAG signals for G-LAN and PCIE-LAN
REF_CLK+/- 0 Provide 25MHz reference clock when P1 SYS_CON is low