ADLINK nanoX-BT - Manual (Page 16)

Page 16 nanoX-BT
Row A Row B
Pin Name Pin Name
80 GND(FIXED) 80 GND(FIXED)
81 LVDS_A_CK+ / eDP_TX3+ 81 DDI0_PAIR3+
82 LVDS_A_CK- / eDP_TX3- 82 DDI0_PAIR3-
83 LVDS_I2C_CK / eDP_AUX+ 83 LVDS_/eDP_BKLT_CTRL
84 LVDS_I2C_DAT / eDP_AUX- 84 VCC_5V_SBY
85 GPI3 85 VCC_5V_SBY
86 RSVD 86 VCC_5V_SBY
87 eDP_HPD 87 VCC_5V_SBY
88 PCIE_CLK_REF+ 88 BIOS_DIS1#
89 PCIE_CLK_REF- 89 DD0_HPD
90 GND(FIXED) 90 GND(FIXED)
91 SPI_POWER 91 DDI0_PAIR5+
92 SPI_MISO 92 DDI0_PAIR5-
93 GPO0 93 DDI0_PAIR6+
94 SPI_CLK 94 DDI0_PAIR6-
95 SPI_MOSI 95 DDI0_DDC_AUX_SEL
96 TPM_PP 96 USB_HOST_PRSNT
97 TYPE10# 97 SPI_CS#
98 SER0_TX 98 DDI0_CTRLCLK_AUX+
99 SER0_RX 99 DDI0_CTRLDATA_AUX-
100 GND(FIXED) 100 GND(FIXED)
101 SER1_TX / CAN_TX 101 FAN_PWMOUT
102 SER1_RX / CAN_RX 102 FAN_TACHIN
103 LID# 103 SLEEP#
104 VCC_12V 104 VCC_12V
105 VCC_12V 105 VCC_12V
106 VCC_12V 106 VCC_12V
107 VCC_12V 107 VCC_12V
108 VCC_12V 108 VCC_12V
109 VCC_12V 109 VCC_12V
110 GND(FIXED) 110 GND(FIXED)
Notes:
- LID# and SLEEP# signals are not natively supported on the SOC, they instead connect to GPIO pins simulating their behaviour.
- eDP can be supported by BOM option with loss of LVDS.
- PCIe (port 3) can be supported by BOM option (lose GbE)