Document Outline

• Serial Digital Interface (SDI) MegaCore Function User Guide
  • Contents
  • 1. About This MegaCore Function
    • Features
    • Release Information
    • Device Family Support
    • General Description
      • OpenCore Plus Evaluation
    • Resource Utilization
  • 2. Getting Started
    • Design Flow
    • SDI Walkthrough
      • Creating a New Quartus II Project
      • Launching MegaWizard Plug-In Manager
      • Parameterizing
      • Setting Up Simulation
      • Generating Files
    • Simulating the Design
      • Testbench
      • Simulate with IP Functional Simulation Models
      • Simulating with the ModelSim Simulator
      • Simulating in Third-Party Simulation Tools Using NativeLink
    • Specifying Constraints
      • Single Channel
      • Multiple Channels
    • Compiling the Design
    • Programming a Device
    • Setting Up Licensing
  • 3. Functional Description
    • Block Description
      • Transmitter
        • HD-SDI LN Insertion
        • HD-SDI CRC Generation and Insertion
        • Scrambling and NRZI Coding
        • Transceiver Clock
      • Receiver
        • NRZI Decoding and Descrambling
        • Word Alignment
        • Video Timing Flags Extraction
        • RP168 Switching Compliance
        • HD-SDI LN Extraction
        • HD-SDI CRC Checking
        • Accessing Transceiver
        • Transceiver Clock
      • Transceiver—Soft-Logic Implementation
        • Transmitter
        • Transmitter Clocks
        • Receiver
        • Receiver Clocks
      • Transceiver—Stratix GX Devices
        • Transmitter Clocks
        • Receiver Clocks
        • Transmitter Transceiver Interface
        • Receiver Transceiver Interface
      • Transceiver—Arria GX, Arria II GX, Arria V, Cyclone IV GX, Cyclone V, Stratix II GX, Stratix IV GX, and Stratix V Devices
        • Transmitter Clocks
        • Receiver Clocks
        • Transmitter Transceiver Interface
        • Receiver Transceiver Interface
      • Locking to the Incoming SDI Stream
      • Transceiver Dynamic Reconfiguration for Dual Standard and Triple Standard Receivers
        • Transceiver Dynamic Reconfiguration with Channel Reconfiguration Mode— Arria II GX, HardCopy IV GX, Stratix GX, Stratix II GX, and Stratix IV GX
        • Transceiver Dynamic Reconfiguration with PLL Reconfiguration Mode— Cyclone IV GX
        • Reset Requirement During Reconfiguration
      • OpenCore Plus Time-Out Behavior
    • Signals
    • Parameters
    • MegaCore Verification
  • 4. SDI Audio IP Cores
    • SDI Audio Embed MegaCore Function
      • Functional Description
      • Parameters
      • Signals
      • Register Maps
    • SDI Audio Extract MegaCore Function
      • Functional Description
      • Parameters
      • Signals
      • Register Maps
    • Clocked Audio Input MegaCore Function
      • Parameters
      • Signals
      • Register Maps
    • Clocked Audio Output MegaCore Function
      • Parameters
      • Signals
      • Register Maps
    • AES Format
    • Avalon-ST Audio Interface
    • Instantiating the IP Cores
    • Simulating the Testbench
    • Design Example
      • Components
        • SDI Transmitter P0
        • SDI Duplex
        • Audio Extract
        • AES Output Module
        • AES Input Module
        • Audio Embed P0/P1
        • Video Pattern Generator P0/P1
        • Audio Pattern Generator
        • Ancillary Data Insertion P0/P1
        • Transceiver Dynamic Reconfiguration Control Logic
      • Hardware and Software Requirements
      • Hardware Setup
      • Running the Design Example
        • Transmit SD-SDI with Embedding of Audio Group 1
        • Transmit HD-SDI with Embedding of Audio Group 1 and 2
        • Transmit 3G-SDI Level A with Embedding of Audio Group 1, 2 and 3
        • Transmit 3G-SDI Level B with Embedding of Audio Group 1, 2, 3 and 4
  • A. Constraints
    • Specifying TimeQuest Timing Analyzer Constraints
      • Specify Clock Characteristics
      • Set Multicycle Paths
      • Specify Clocks that are Exclusive or Asynchronous
      • Define the Setup and Hold Relationship between 135-MHz Clocks and 337.5-MHz Zero-degree Clocks
      • Minimize Timing Skew
    • Constraints for the SDI Soft Transceiver
      • Non Cyclone Devices
        • Classic Timing Analyzer
        • TimeQuest Timing Analyzer
      • Cyclone Devices Only
        • Classic Timing Analyzer
        • TimeQuest Timing Analyzer
  • B. Clocking
  • C. Receive and Retransmit
    • Loopback FIFO Buffer
  • Additional Information
    • Document Revision History
    • How to Contact Altera
    • Typographic Conventions