Altera PHYLite - Manual (Page 18)

<variation_name>.sdc
You can find the location of the <variation_name>.sdc file in the .qip, which is generated during the IP
generation. The <variation_name>.sdc allows the Fitter to optimize timing margins with timing driven
compilation and allows the TimeQuest timing analyzer to analyze the timing of your design.
The IP core uses <variation_name>.sdc for the following operations:
• Creating clocks on PLL inputs
• Creating generated clocks
• Calling
derive_clock_uncertainty
• Creating
set_output_delay
and
set_input_delay
constraints to analyze the timing of the read and
write paths
<variation_name>_ip_parameters.tcl
The <variation_name>_ip_parameters.tcl file lists the Altera PHYLite for Parallel Interfaces IP core
parameters and is read by the <variation_name>.sdc.
<variation_name>_pin_map.tcl
The <variation_name>_pin_map.tcl is a TCL library of functions and procedures that
<variation_name>.sdc uses.
Timing Analysis
Table 10: Timing Analysis
This table lists the timing analysis performed in the I/O and FPGA for the Altera PHYLite for Parallel Interfaces
IP core.
Location Description
I/O The Altera PHYLite for Parallel Interfaces IP core generation creates the appropriate
generated clock settings for the read strobe on the read path and the write strobe of the write
path, according to their strobe type (singled-ended, complementary, or differential) and their
interface type (SDR or DDR) in the following format:
• Clock name for read strobe—
<pin_name>_IN
.
• Clock name for the write path—
<pin_name>
for positive strobe.
• Clock name for the write path—
<pin_name>_neg
for negative strobe.
The
set_false_path
,
set_input_delay
and
set_output_delay
constraints are also
generated to ensure proper timing analysis of the Altera PHYLite for Parallel Interfaces IP
core.
18 <variation_name>.sdc
ug_altera_phylite
2015.01.16
Altera Corporation Altera PHYLite for Parallel Interfaces IP Core User Guide
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