Altera PHYLite - Manual (Page 25)

VCO Multiplication
Factor
Core Rate
Minimum Interpolator
Phase
Maximum Interpolator Phase
2
Full 0x180 0xFFF
Half 0x100 0xFFF
Quarter 0x380 0xFFF
4
Full 0x200 0xFFF
Half 0x100 0xFFF
Quarter 0x280 0xFFF
8
Full 0x200 0xFFF
Half 0x000 0xFFF
Quarter 0x380 0xFFF
Address Look-Up
You must know the lane addresses and the pin placement to address an interface correctly. Because these
values are placement dependent, these values will be different before and after placement. The Altera
PHYLite for Parallel Interfaces IP core is generated as if the IP core is the only IP core in a column, with
lane addresses starting from 0. If the IP core is placed in a column containing Arria 10 External Memory
Interfaces or Altera PHYLite for Parallel Interfaces IP cores (with dynamic reconfiguration), then the
addressing of the I/O lanes in the interfaces must be modified to avoid conflicts. A pin can also be moved
into any lane within a group. In general, even if the Altera PHYLite for Parallel Interfaces IP core interface
is the only IP in the column, the Fitter will still modify the addresses.
ug_altera_phylite
2015.01.16
Address Look-Up 25
Altera PHYLite for Parallel Interfaces IP Core User Guide Altera Corporation
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