Altera CPRI v6.0 MegaCore Function - Manual (Page 25)

User logic must provide the connection. Refer to the demonstration testbench for example working user
logic including one correct method to instantiate and connect the external PLL to a single CPRI v6.0 IP
core.
Related Information
Interface to the External PLL on page 3-48
Altera Transceiver PHY IP Core User Guide
Information about how to configure an external PLL for your Arria V GZ or Stratix V design.
Arria 10 Transceiver PHY User Guide
Information about how to configure an external PLL for your own Arria 10 design.
Adding the External Reset Controller
The CPRI v6.0 IP core requires that you provide reset control logic to handle the required reset sequence
for the IP core transceiver on the device. Altera recommends that you generate and connect two Altera
Transceiver PHY Reset Controller IP cores to perform this function, one reset controller for the TX
transceiver and data path and one reset controller for the RX transceiver and data path in the CPRI v6.0
IP core. If you do not implement the device-specific correct reset sequence, the IP core does not function
correctly in hardware.
You can use the IP Catalog to generate Altera Transceiver PHY Reset Controller IP cores for the device
family that your CPRI v6.0 IP core targets.
Follow the instructions in the Altera Transceiver PHY IP Core User Guide or the Arria 10 Transceiver PHY
User Guide. The CPRI v6.0 IP core configures the Native PHY IP core for the target device family. You
must configure the reset controllers to coordinate reset of the CPRI v6.0 IP core including the Native PHY
IP core, and the external PLL IP core. In the case of Arria V GZ and Stratix V variations, the reset control‐
lers must also coordinate with the transceiver reconfiguration controller.
To configure a TX reset controller, in the Altera Transceiver PHY Reset Controller parameter editor, you
must set the following parameter values:
• Set Input clock frequency to a value in the range of 100–150.
• Turn on Synchronize reset input.
• Turn on Use fast reset for simulation.
• Turn on Enable TX PLL reset control.
• Set pll_powerdown duration to the value of 10.
• Turn on Enable TX channel reset control.
• Leave all other parameters turned off or for the parameters that do not turn on or off, at their default
values.
To configure an RX reset controller, in the Altera Transceiver PHY Reset Controller parameter editor,
you must set the following parameter values:
• Set Input clock frequency to a value in the range of 100–150.
• Turn on Synchronize reset input.
• Turn on Use fast reset for simulation.
• Turn on Enable RX channel reset control.
• Leave all other parameters turned off or for the parameters that do not turn on or off, at their default
values.
2-14 Adding the External Reset Controller
UG-01156
2014.08.18
Altera Corporation Getting Started with the CPRI v6.0 IP Core
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