Altera Cyclone V GX FPGA - Manual (Page 21)

Chapter 6: Board Test System 6–5
Using the Board Test System
October 2012 Altera Corporation Cyclone V GX FPGA Development Kit
User Guide
1 If you plug in an external USB-Blaster cable to the JTAG header (J13), the On-Board
USB-Blaster II is disabled.
1 JTAG DIP switch bank (SW5) selects which interfaces are in the chain. Refer to
Table 4–3 on page 4–3 for detailed settings.
f
For details on the JTAG chain, refer to the Cyclone V GX FPGA Development Board
Reference Manual. For USB-Blaster II configuration details, refer to the On-Board
USB-Blaster II page.
Qsys Memory Map
The Qsys memory map control shows the memory map of the Qsys system on your
board.
The GPIO Tab
The GPIO tab allows you to interact with all the general purpose user I/O
components on your board. You can write to the character LCD, read DIP switch
settings, turn LEDs on or off, run a server program on the Ethernet port, and detect
push button presses.
Figure 6–2 shows the GPIO tab.
Figure 6–2. The GPIO Tab