Altera Cyclone V SoC - Manual (Page 14)

3–4 Chapter 3: Development Board Setup
Factory Default Switch and Jumper Settings
Cyclone V SoC Development Kit November 2013 Altera Corporation
User Guide
3. Set the DIP switch bank (SW4) to match Table 3–3 and Figure 3–1 .
In the following table, up and down indicates the position of the switch with the
board orientation as shown in
Figure 3–1 .
4. Set the following jumper blocks to match Table 3–4 and Figure 3–1 .
Table 3–3. SW4 JTAG DIP Switch Settings
Switch
Board
Label
Function
Default
Position
1 HPS
■ ON (up) = Do not Include HPS in the JTAG chain.
■ OFF (down) = Include HPS in the JTAG chain
OFF
2 FPGA
■ ON (up) = Do not Include the FPGA in the JTAG
chain.
■ OFF (down) = Include the FPGA in the JTAG chain.
OFF
3 HSMC
■ ON (up) = Do not include the HSMC connector in the
JTAG chain.
■ OFF (down) = Include the HSMC connector in the
JTAG chain.
ON
4 MAX
■ ON (up) = Do not include the MAX V system
controller in the JTAG chain.
■ OFF (down) = Include the MAX V system controller in
the JTAG chain.
OFF
Table 3–4. Default Jumper Settings
Board
Reference
Board Label Description
Default
Position
J5 9V
■ SHORT: Powers the CFI flash memory device
using a 9 V supply for fast write in
manufacturing.
■ OPEN: Powers CFI flash memory from the
default 3 V supply.
OPEN
J6 JTAG HPS SEL
■ SHORT: Controls the HPS from On-Board USB
Blaster II JTAG master.
■ OPEN: Controls the HPS from MICTOR-based
JTAG master, such as DSTREAM or Lauterbach
programming cables. Also, set SW4.1 to ON to
remove the On-Board USB Blaster II from
driving the HPS JTAG input port in this mode.
SHORT
J7 JTAG SEL
■ SHORT: The USB Blaster II is the source of the
JTAG chain.
■ OPEN: The Mictor is the source of the JTAG
chain.
SHORT
J13 OSC1_CLK_SEL
■ SHORT: Selects the on board 25MHz clock.
■ OPEN: Selects SMA.
SHORT