Altera Cyclone V SoC - Manual (Page 30)

5–12 Chapter 5: Board Test System
Using the Board Test System
Cyclone V SoC Development Kit November 2013 Altera Corporation
User Guide
Data Test
This group displays information about the SDI interface test when running in PRBS
mode in the patter generator.
■ Data rate —Displays the current SDI data rate in megabytes per second (MBps).
■ Freq —Displays the data rate frequency in MHz which is equivalent to Mbps.
■ Bits —Displays the number of bits transmitted since clicking Start.
■ Inserted errors —Displays the number of errors inserted by clicking Insert Error
button.
■ Detected errors —Displays the number of bit errors detected by the error checking
circuitry.
■ BER —Displays the bit error rate of the interface.
■ PLL lock —Displays Yes if the SDI PLL is locked.
■ Pattern Sync —Displays Yes if the receiver has detected the input data pattern.
■ Start— Starts the PRBS data test and begins to monitor and update screen with
live test results.
■ Stop —Stops the PRBS data test.
■ Insert Error —Inserts an error into an SDI data stream that is detected by the
receiver when in loopback using the included video cable.
■ Clear —Clears the Detected errors counter.
■ PMA Setting —Opens the PMA settings window that allows for adjusting the
analog transceiver settings, such as output voltage, loopback settings, and
equalization.
■ PRBS (list)—Selects the transmit pattern and sets the receive error detection
circuitry to expect the same pattern for use in loopback testing.