Altera Internal Memory (RAM and ROM) IP Core User Manual
Page 10
The new parameter editor appears when the generation is complete.
4. Click Generate HDL, and then confirm the Synthesis and Simulation file options. Verilog is the
parameter editor default HDL for synthesis files. If your original IP core was generated for VHDL,
select VHDL to retain the original output HDL format.
5. To regenerate the new IP variation for the new target device, click Generate. When generation is
complete, click Close.
6. Click Finish to complete migration of the IP core. Click OK if you are prompted to overwrite IP core
files. The Device Family column displays the migrated device support. The migration process replaces
<my_ip>
.qip
with the <my_ip>
.qsys
top-level IP file in your project.
Note: If migration does not replace <my_ip>
.qip
with <my_ip>
.qsys
, click Project > Add/Remove
Files in Project to replace the file in your project.
7. Review the latest parameters in the parameter editor or generated HDL for correctness. IP migration
may change ports, parameters, or functionality of the IP core. During migration, the IP core's HDL
generates into a library that is different from the original output location of the IP core. Update any
assignments that reference outdated locations. If your upgraded IP core is represented by a symbol in a
supporting Block Design File schematic, replace the symbol with the newly generated <my_ip>
.bsf
after migration.
Note: The migration process may change the IP variation interface, parameters, and functionality.
This may require you to change your design or to re-parameterize your variant after the
Upgrade IP Components dialog box indicates that migration is complete. The Description
field identifies IP cores that require design or parameter changes.
Related Information
UG-01068
2014.12.17
Migrating IP Cores to a Different Device
2-5
Customizing Embedded Memory IP Cores
Altera Corporation