Altera Internal Memory (RAM and ROM) IP Core - Manual (Page 32)

Parameter Legal Values Description
Which ports should be registered?
The following options are available:
• ‘data’ and ‘wren’ input ports
• ‘address’ input port
• ‘q’ output port
On/Off Specifies whether to register the
input and output ports.
Create one clock enable signal for each
clock signal. Note: All registered ports are
controlled by the enable signal(s)
On/Off Specifies whether to turn on the
option to create one clock
enable signal for each clock
signal.
More Options
Use clock enable for
port A input registers
On/Off Specifies whether to use clock
enable for port A input registers.
Use clock enable for
port A output registers
On/Off Specifies whether to use clock
enable for port A output
registers.
Create an
‘addressstall_a’ input
port.
On/Off Specifies whether to create a
addressstall_a input port. You
can create this port to act as an
extra active low clock enable
input for the address registers.
Create byte enable for port A On/Off Specifies whether to create a
byte enable for port A. Turn on
this option if you want to mask
the input data so that only
specific bytes, nibbles, or bits of
data are written.
To enable byte enable for port A
and port B, the data width ratio
has to be 1 or 2 for the RAM: 1-
PORT and RAM: 2-PORT IP
cores.
What is the width of a byte for byte
enables?
• MLAB: 5 or 10
• Other memory block
types: 8 or 9
• M10K and M20K: 8, 9,
or 10
Specifies the byte width of the
byte enable port. The width of
the data input port must be
divisible by the byte size.
Create an ‘aclr’ asynchronous clear for the
registered ports.
On/Off Specifies whether to create an
asynchronous clear port for the
registered data, wren, address, q,
and byteena_a ports.
UG-01068
2014.12.17
RAM:1-Port IP Core Parameters 4-7
Embedded Memory Signals and Parameters Altera Corporation
Send Feedback