Altera PowerPlay Early Power Estimator - Manual (Page 20)

3–8 Chapter 3: Using Cyclone III PowerPlay Early Power Estimator
PowerPlay Early Power Estimator Inputs
PowerPlay Early Power Estimator User Guide for Cyclone III FPGAs © June 2009 Altera Corporation
Port A – Clock Freq
(MHz) Enter the clock frequency for Port A of the RAM block or blocks in MHz. This value is limited by
the maximum frequency specification for the RAM type and device family.
Port A – Enable % Enter the average percentage of time the input clock enable for Port A is active, regardless of
activity on RAM data and address inputs. The enable percentage ranges from 0 to 100%. The
default is 25%.
RAM power is primarily consumed when a clock event occurs. Using a clock enable signal to
disable a port when no read or write operation is occurring can result in significant power
savings.
Port A – Write % Enter the average percentage of time Port A of the RAM block is in write mode as opposed to
read mode. For simple dual-port (one read or one write) RAMs, the write port (A) is inactive
when not executing a write. For single-port and true dual-port RAMs, Port A reads when not
written to. This field is ignored for RAMs in ROM mode.
This value must be a percentage number between 0% and 100%. The default is 50%.
Port B – Clock Freq
(MHz) Enter the clock frequency for Port B of the RAM block or blocks in MHz. This value is limited by
the maximum frequency specification for the RAM type and device family. Port B is ignored for
RAM blocks in ROM or single-port mode.
Port B – Enable % Enter the average percentage of time the input clock enable for Port B is active, regardless of
activity on RAM data and address inputs. The enable percentage ranges from 0 to 100%. The
default is 25%. Port B is ignored for RAM blocks in ROM or single-port mode.
RAM power is primarily consumed when a clock event occurs. Using a clock enable signal to
disable a port when no read or write operation is occurring can result in significant power
savings.
Port B – R/W % For RAM blocks in true dual-port mode, enter the average percentage of time Port B of the RAM
block is in write mode as opposed to read mode. For RAM blocks in simple dual-port mode,
enter the percentage of time Port B of the RAM block is reading. You cannot write to Port B in
simple dual-port mode. Port B is ignored for RAM blocks in ROM or single-port mode.
This value must be a percentage number between 0% and 100%. The default is 50%.
Toggle % The average percentage for how often each block output signal changes value on each enabled
clock cycle is multiplied by the clock frequency and enable percentage to determine the number
of transitions per second. This only affects routing power.
50% corresponds to a randomly changing signal. A random signal changes states only half the
time.
Thermal Power (W),
Routing
This shows the power dissipation due to estimated routing (in W).
Routing power is highly dependent on placement and routing, which is itself a function of design
complexity. The values shown are representative of routing power based on experimentation
across over 100 customer designs.
Use the Quartus II PowerPlay Power Analyzer for detailed analysis based on the routing used in
your design. This value is calculated automatically.
Thermal Power (W),
Block This shows the power dissipation due to internal toggling of the RAM (in W).
Use the Quartus II PowerPlay Power Analyzer for accurate analysis based on the exact RAM
modes in your design. This value is automatically calculated.
Thermal Power (W),
Total This shows the estimated power in W, based on the inputs you entered. It is the total power
consumed by RAM blocks and is equal to the routing power and the block power. This value is
automatically calculated.
User Comments Enter any comments. This is an optional entry.
Table 3–3. RAM Selection Information (Part 2 of 2)
Parameter Description