Altera PowerPlay Early Power Estimator - Manual (Page 28)

3–16 Chapter 3: Using Cyclone III PowerPlay Early Power Estimator
PowerPlay Early Power Estimator Inputs
PowerPlay Early Power Estimator User Guide for Cyclone III FPGAs © June 2009 Altera Corporation
Figure 3–9 shows the PLL Summary in the Quartus II software Compilation Report
for a design targeting a Cyclone III device. The Compilation Report provides the VCO
frequency of a PLL.
Figure 3–10 shows the PLL section of the PowerPlay Early Power Estimator and the
estimated power consumed by PLLs.
Clocks
Cyclone III device family have up to 20 global clock networks.
Each row in the Clocks section represents a clock network or a separate clock domain.
You must enter the clock frequency (f
MAX
) in MHz and the total fan-out for each clock
network used.
Figure 3–9. PLL Summary in Compilation Report
Figure 3–10. PLL Section in the PowerPlay Early Power Estimator