Document Outline

• RapidIO MegaCore Function v14.0 and v14.0 Arria 10 Edition User Guide
  • Contents
  • 1. About This MegaCore Function
    • Features
      • New Features in the RapidIO IP Core v14.0 and v14.0 Arria 10 Edition Releases
      • RapidIO IP Core Features
      • Supported Transactions
    • Device Family Support
    • IP Core Verification
      • Simulation Testing
      • Hardware Testing
      • Interoperability Testing
    • Performance and Resource Utilization
    • Release Information
    • Installation and Licensing
      • OpenCore Plus Evaluation
      • OpenCore Plus Time-Out Behavior
  • 2. Getting Started
    • Customizing and Generating IP Cores
    • Files Generated for Altera IP Cores (Legacy Parameter Editor)
    • Files Generated for Altera IP Cores
    • Simulating IP Cores
      • Simulating the Testbench with the ModelSim Simulator
      • Simulating the Testbench with the VCS Simulator
    • Integrating Your IP Core in Your Design
      • Calibration Clock
      • Dynamic Transceiver Reconfiguration Controller
      • Transceiver Settings
      • Adding Transceiver Analog Settings for Arria II GX, Arria II GZ, and Stratix IV GX Variations
      • External Transceiver PLL
    • Specifying Constraints
    • Compiling the Full Design and Programming the FPGA
    • Instantiating Multiple RapidIO IP Cores
      • Clock and Signal Requirements for Arria V, Cyclone V, and Stratix V Variations
      • Clock and Signal Requirements for Arria II GX, Arria II GZ, Cyclone IV GX, and Stratix IV GX Variations
      • Correcting the Synopsys Design Constraints File to Distinguish RapidIO IP Core Instances
      • Sourcing Multiple Tcl Scripts for non-Arria 10 Variations
  • 3. Parameter Settings
    • Physical Layer Settings
      • Device Options
        • Mode Selection
        • Transceiver Selection
        • Enable Transceiver Dynamic Reconfiguration
        • Synchronizing Transmitted ackID
        • Sending Link-Request Reset-Device on Fatal Errors
        • Number of Link-Request Attempts Before Declaring Fatal Error
      • Data Settings
        • Baud Rate
        • Reference Clock Frequency
        • Receive Buffer Size
        • Transmit Buffer Size
      • Receive Priority Retry Thresholds
    • Transport and Maintenance Settings
      • Transport Layer
        • Enable 16-Bit Device ID Width
        • Enable Avalon-ST Pass-Through Interface
        • Destination ID Checking
      • Input/Output Maintenance Logical Layer Module
        • Maintenance Logical Layer
        • Transmit Address Translation Windows
      • Port Write
        • Port Write Tx Enable
        • Port Write Rx Enable
    • I/O and Doorbell Settings
      • I/O Logical Layer Interfaces
      • I/O Slave Address Width
      • I/O Read and Write Order Preservation
      • Avalon-MM Master
      • Avalon-MM Slave
      • Doorbell Slave
    • Capability Registers Settings
      • Device Registers
        • Device ID
        • Vendor ID
        • Revision ID
      • Assembly Registers
        • Assembly ID
        • Assembly Vendor ID
        • Assembly Revision ID
        • Extended Features Pointer
      • Processing Element Features
        • Bridge Support
        • Memory Access
        • Processor Present
      • Switch Support
        • Enable Switch Support
        • Number of Ports
        • Port Number
      • Data Messages
        • Source Operation
        • Destination Operation
  • 4. Functional Description
    • Interfaces
      • RapidIO Interface
      • Avalon Memory Mapped (Avalon-MM) Master and Slave Interfaces
        • Avalon-MM Interface Widths in the RapidIO IP Core
        • Avalon-MM Interface Byte Ordering
      • Avalon Streaming (Avalon-ST) Interface
    • Clocking and Reset Structure
      • RapidIO IP Core Clocking
        • Avalon System Clock
        • Reference Clock
        • Other Input Clocks
        • Clock Domains
        • Baud Rates and Clock Frequencies
      • Reset for RapidIO IP Cores
        • General RapidIO Reset Signal Requirements
        • Reset Controller
        • Reset Requirements for Arria V, Cyclone V, and Stratix V Variations
        • Reset Requirements for Arria 10 Variations
        • RapidIO IP Core Reset Behavior
    • Physical Layer
      • Features
      • Physical Layer Architecture
      • Low-level Interface Receiver
        • Receiver Transceiver
        • CRC Checking and Removal
      • Low-Level Interface Transmitter
        • Transmitter Transceiver
      • Protocol and Flow Control Engine
      • Physical Layer Receive Buffer
        • Error Conditions that Flush the Receive Buffer
        • Error Conditions Flagged for the Transport Layer
        • Receive Priority Threshold Values
      • Physical Layer Transmit Buffer
        • Transmit and Retransmit Queues
        • Error Conditions that Flush the Transmit Buffer
        • Forced Compensation Sequence Insertion
    • Transport Layer
      • Receiver
      • Transaction ID Ranges
      • Transmitter
    • Logical Layer Modules
      • Concentrator Register Module
      • Maintenance Module
        • Maintenance Register
        • Maintenance Slave Processor
        • Maintenance Master Processor
        • Port-Write Processor
        • Maintenance Module Error Handling
      • Input/Output Logical Layer Modules
        • Input/Output Avalon-MM Master Module
        • RapidIO Packet Data wdptr and Data Size Encoding in Avalon-MM Transactions
        • Input/Output Avalon-MM Master Module Timing Diagrams
        • Input/Output Avalon-MM Slave Module
        • Avalon-MM Burstcount and Byteenable Encoding in RapidIO Packets
        • Input/Output Avalon-MM Slave Module Timing Diagrams
      • Doorbell Module
        • Doorbell Module Block Diagram
        • Preserving Transaction Order
        • Doorbell Message Generation
        • Doorbell Message Reception
      • Avalon-ST Pass-Through Interface
        • Pass-Through Interface Examples
    • Error Detection and Management
      • Physical Layer Error Management
        • Protocol Violations
        • Fatal Errors
      • Logical Layer Error Management
        • Maintenance Avalon-MM Slave
        • Maintenance Avalon-MM Master
        • Port-Write Reception Module
        • Port-Write Transmission Module
        • Input/Output Avalon-MM Slave
        • Input/Output Avalon-MM Master
      • Avalon-ST Pass-Through Interface
  • 5. Signals
    • Physical Layer Signals
      • Status Packet and Error Monitoring Signals
      • Multicast Event Signals
      • Receive Priority Retry Threshold-Related Signals
      • Physical Layer Buffer Status Signals
      • Transceiver Signals
      • Register-Related Signals
    • Transport and Logical Layer Signals
      • Avalon-MM Interface Signals
      • Avalon-ST Pass-Through Interface Signals
      • Error Management Extension Signals
      • Packet and Error Monitoring Signal for the Transport Layer
  • 6. Software Interface
    • Physical Layer Registers
    • Transport and Logical Layer Registers
      • Capability Registers (CARs)
      • Command and Status Registers (CSRs)
      • Maintenance Interrupt Control Registers
      • Receive Maintenance Registers
      • Transmit Maintenance Registers
      • Transmit Port-Write Registers
      • Receive Port-Write Registers
      • Input/Output Master Address Mapping Registers
      • Input/Output Slave Mapping Registers
      • Input/Output Slave Interrupts
      • Transport Layer Feature Register
      • Error Management Registers
      • Doorbell Message Registers
  • 7. Testbenches
    • Reset, Initialization, and Configuration
    • Maintenance Write and Read Transactions
    • SWRITE Transactions
    • NWRITE_R Transactions
    • NWRITE Transactions
    • NREAD Transactions
    • Doorbell Transactions
    • Doorbell and Write Transactions With Transaction Order Preservation
    • Port-Write Transactions
    • Transactions Across the Avalon-ST Pass-Through Interface
  • 8. Qsys Design Example
    • Creating a New Quartus II Project
    • Running Qsys
      • Adding and Parameterizing the RapidIO Component
      • Adding and Connecting Other System Components
        • Adding the Master Maintenance BFM
        • Adding the Master I/O BFM
        • Adding the On-Chip Memory
      • Connecting Clocks and the System Components
        • Connecting Unconnected Clocks
        • Connecting System Components
        • Assigning Addresses and Setting the Clock Frequency
      • Generating the System
    • Simulating the System
  • A. Initialization Sequence
  • C. Porting a RapidIO Design from the Previous Version of the Software
    • Upgrading a RapidIO Design Without Changing Device Family
    • Upgrading a RapidIO Design to the Arria 10 Device Family
  • Additional Information
    • Document Revision History
    • How to Contact Altera
    • Typographic Conventions