Altera 100G Development Kit, Stratix IV GT Edition - Manual (Page 50)

2–42 Chapter 2: Board Components
Components and Interfaces
100G Development Kit, Stratix IV GT Edition Reference Manual September 2010 Altera Corporation
CFP Interface
The CFP interface consists of 10 full-duplex transceiver channels. One of the CFP
modules that the Stratix IV GT 100G development board interfaces with is the Reflex
Photonics CFP 100G optical module.
Table 2–33 lists the pin assignments for the CFP interface and their corresponding
schematic signal names and Stratix IV GT pin numbers.
Table 2–33. CFP Interface Pin Assignments, Schematic Signal Names, and Functions (Part 1 of 3)
Board
Reference
Description
Schematic
Signal Name
i/O Standard
Stratix IV GT
Device
Pin Name
Other
Connections
J37.113 Transmit XCVR pair 0 from FPGA CFP_TX_P0
1.2-V PCML
AN4 —
J37.114 Transmit XCVR pair 0 from FPGA CFP_TX_N0 AN3 —
J37.116 Transmit XCVR pair 1 from FPGA CFP_TX_P1 AL4 —
J37.117 Transmit XCVR pair 1 from FPGA CFP_TX_N1 AL3 —
J37.119 Transmit XCVR pair 2 from FPGA CFP_TX_P2 AE4 —
J37.120 Transmit XCVR pair 2 from FPGA CFP_TX_N2 AE3 —
J37.122 Transmit XCVR pair 3 from FPGA CFP_TX_P3 AC4 —
J37.123 Transmit XCVR pair 3 from FPGA CFP_TX_N3 AC3 —
J37.125 Transmit XCVR pair 4 from FPGA CFP_TX_P4 AA4 —
J37.126 Transmit XCVR pair 4 from FPGA CFP_TX_N4 AA3 —
J37.128 Transmit XCVR pair 5 from FPGA CFP_TX_P5 W4 —
J37.129 Transmit XCVR pair 5 from FPGA CFP_TX_N5 W3 —
J37.131 Transmit XCVR pair 6 from FPGA CFP_TX_P6 N4 —
J37.132 Transmit XCVR pair 6 from FPGA CFP_TX_N6 N3 —
J37.134 Transmit XCVR pair 7 from FPGA CFP_TX_P7 L4 —
J37.135 Transmit XCVR pair 7 from FPGA CFP_TX_N7 L3 —
J37.137 Transmit XCVR pair 8 from FPGA CFP_TX_P8 J4 —
J37.138 Transmit XCVR pair 8 from FPGA CFP_TX_N8 J3 —
J37.140 Transmit XCVR pair 9 from FPGA CFP_TX_P9 G4 —
J37.141 Transmit XCVR pair 9 from FPGA CFP_TX_N9 G3 —
J37.79 Receive XCVR pair 0 to FPGA CFP_RX_P0 AP2 —
J37.80 Receive XCVR pair 0 to FPGA CFP_RX_N0 AP1 —
J37.82 Receive XCVR pair 1 to FPGA CFP_RX_P1 AM2 —
J37.83 Receive XCVR pair 1 to FPGA CFP_RX_N1 AM1 —
J37.85 Receive XCVR pair 2 to FPGA CFP_RX_P2 AF2 —
J37.86 Receive XCVR pair 2 to FPGA CFP_RX_N2 AF1 —
J37.88 Receive XCVR pair 3 to FPGA CFP_RX_P3 AD2 —
J37.89 Receive XCVR pair 3 to FPGA CFP_RX_N3 AD1 —
J37.91 Receive XCVR pair 4 to FPGA CFP_RX_P4 AB2 —
J37.92 Receive XCVR pair 4 to FPGA CFP_RX_N4 AB1 —
J37.94 Receive XCVR pair 5 to FPGA CFP_RX_P5 Y2 —
J37.95 Receive XCVR pair 5 to FPGA CFP_RX_N5 Y1 —