Altera 100G Development Kit, Stratix IV GT Edition - Manual (Page 68)

2–60 Chapter 2: Board Components
Components and Interfaces
100G Development Kit, Stratix IV GT Edition Reference Manual September 2010 Altera Corporation
U48.L2 Read data bus QDR2B_Q15 U44.AV18 —
U48.N3 Read data bus QDR2B_Q16 U44.AV19 —
U48.P3 Read data bus QDR2B_Q17 U44.AT19 —
— Stratix IV GT RDN pin for calibrated-termination QDR2B_RDN U44.A26 —
U48.A8 Read port select QDR2B_RPSN U44.BD16 —
— Stratix IV GT RUP pin for calibrated-termination QDR2B_RUP U44.B25 —
U48.A4 Write port select QDR2B_WPSN U44.BC14 —
QDR II C Interface
U49.R9 Address bus QDR2C_A0 U44.AL39 —
U49.R8 Address bus QDR2C_A1 U44.AM39 —
U49.B4 Address bus QDR2C_A2 U44.AT25 —
U49.B8 Address bus QDR2C_A3 U44.AM24 —
U49.C5 Address bus QDR2C_A4 U44.AR25 —
U49.C7 Address bus QDR2C_A5 U44.AN24 —
U49.N5 Address bus QDR2C_A6 U44.AT24 —
U49.N6 Address bus QDR2C_A7 U44.AL35 —
U49.N7 Address bus QDR2C_A8 U44.AK38 —
U49.P4 Address bus QDR2C_A9 U44.AL23 —
U49.P5 Address bus QDR2C_A10 U44.AN23 —
U49.P7 Address bus QDR2C_A11 U44.AJ39 —
U49.P8 Address bus QDR2C_A12 U44.AM38 —
U49.R3 Address bus QDR2C_A13 U44.AM21 —
U49.R4 Address bus QDR2C_A14 U44.AM22 —
U49.R5 Address bus QDR2C_A15 U44.AU23 —
U49.R7 Address bus QDR2C_A16 U44.AK39 —
U49.A9 Address bus QDR2C_A17 U44.AM25 —
U49.A3 Address bus QDR2C_A18 U44.AM23 —
U49.A10 Address bus QDR2C_A19 U44.AH31 —
U49.C6 Address bus QDR2C_A20 U44.AP25 —
U49.B7 Byte write select QDR2C_BWSN0 U44.AM27 —
U49.A5 Byte write select QDR2C_BWSN1 U44.AM26 —
U49.A1 QDR II echo clock QDR2C_CQ_N U44.AD26 —
U49.A11 QDR II echo clock QDR2C_CQ_P U44.BA29 —
U49.P10 Write data bus QDR2C_D0 U44.AT29 —
U49.N11 Write data bus QDR2C_D1 U44.AN28 —
U49.M11 Write data bus QDR2C_D2 U44.AR29 —
U49.K10 Write data bus QDR2C_D3 U44.AV29 —
U49.J11 Write data bus QDR2C_D4 U44.AU29 —
Table 2–39. QDR II Interface Pin Assignments, Schematic Signal Names, and Functions (Part 5 of 8)
Board
Reference
Description
Schematic
Signal Name
Stratix IV GT
Device
Pin Name
Other
Connections