Zilog Z8F0130 User Manual
Page 78
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eZ8
™
CPU Core
User Manual
UM012820-0810
eZ8
™
CPU Instruction Set Summary
63
EI
Enable Interrupts
IRQCTL[7]
1
9F
– – – – – –
1
2
HALT
Halt Mode
7F
– – – – – –
1
2
INC dst
dst
dst + 1
R
20
– * * * – –
2
2
IR
21
2
3
r
0E–FE
1
2
INCW dst
dst
dst + 1
RR
A0
– * * * – –
2
5
IR
A1
2
6
IRET
FLAGS
@SP
SP
SP + 1
PC
@SP
SP
SP + 2
IRQCTL[7]
1
BF
* * * * * *
1
5
JP dst
PC
dst
DA
8D
– – – – – –
3
2
IRR
C4
2
3
JP cc, dst
if cc is true
PC
dst
DA
0D–FD – – – – – –
3
2
JR dst
PC
PC + X
RA
8B
– – – – – –
2
2
JR cc, dst
if cc is true
PC
PC + X
RA
0b–FB – – – – – –
2
2
Table 20. eZ8 CPU Instruction Summary (Continued)
Assembly
Mnemonic
Symbolic
Operation
Address
Mode
Op
Code(s)
(Hex)
Flags
Fetch
Cycles
Instr.
Cycles
dst src
C Z S V D H
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