Zilog EZ80L92 - Manual (Page 83)

eZ80L92 Development Kit
User Manual
UM012913-0407 General Array Logic Equations
79
A5 /* synthesis loc="P13"*/,
A6 /* synthesis loc="P27"*/,
A7 /* synthesis loc="P26"*/,
nIORQ /* synthesis loc="P2"*/,
nRD /* synthesis loc="P7"*/,
nCS /* synthesis loc="P25"*/, //CS3 for CS9800
nWR /* synthesis loc="P9"*/,
nMEMRQ /* synthesis loc="P16"*/;
output
nEM_RD /* synthesis loc="P17"*/,
nEM_WR /* synthesis loc="P18"*/,
nCT_WR /* synthesis loc="P19"*/,
nAN_WR /* synthesis loc="P20"*/,
nDIS_ETH /* synthesis loc="P21"*/;
parameter anode=8'h00;
parameter cathode=8'h01;
parameter latch=8'h02;
wire [7:0] address={A7,A6,A5,A4,A3,A2,A1,A0};
assign nEM_WR =
~((nDIS_EM==1)&(nWR==0)&(nEM_EN==0)&(address==latch));
assign nEM_RD =
~((nDIS_EM==1)&(nRD==0)&(nEM_EN==0)&(address==latch));
assign nAN_WR =
~((nDIS_EM==1)&(nWR==0)&(nEM_EN==0)&(address==anode));
assign nCT_WR =
~((nDIS_EM==1)&(nWR==0)&(nEM_EN==0)&(address==cathode));
assign nDIS_ETH = ~(nCS);
endmodule