Artesyn COMX-P1022 Installation and Use (July 2014) - Manual (Page 58)

Functional Description
COMX-P1022 COM Express Module Installation and Use (6806800M04C) 58
 32 KB instruction and 32 KB data first-level cache (L1) for each core
 256 KB second-level cache (L2) with ECC
 64 bit DDR2/DDR3 controller with ECC supports data rate of up to 667 Mbps per pin
 31x31 mm 689-pin wirebond power-BGA
 45 nm SOI process technology
Each e500 core complex contains a separate 32-KB, eight-way set associative level 1 (L1)
instruction and data caches to provide the execution units and registers rapid access to
instructions and data. The 32 KB cache is divided into eight ways and 128 sets, so there is a
total of 1024 blocks. The size of each block is eight words (32 bytes).
4.3 Memory
P1022 supports 64-bit DDR2/DDR3 SDRAM memory controller with ECC.
The COM-E module supports a 2GB dual-rank DDR3 with ECC SO-UDIMM memory modules
which can be run at 667MHz.
Figure 4-2 P1022 Processor Block Diagram