Fluke Biomedical 960SF-220 - Manual (Page 9)

Theory of Operation
Theory of Operation
2
2-1
Section 2
Theory of Operation
2.1 Theory of Operation
During the following discussion, refer to block diagram, Figure 2-1, and the schematic diagrams in
Appendix B.
2.2 Detector Input Circuitry
Connector J5 is the detector signal input. Input impedance is 50 ohms to match the signal cable and the
detector's output impedance. The input signal is a pulse train that could be positive or negative depending
upon the detector used. Z5 is a unity gain differential amplifier with single ended output whose output is
fed into signal multiplexer Z6. Z6 selects detector input or test input, depending on the setting of the test
switch. The signal is then fed into the discriminator.
2.3 Discriminator
The function of the discriminator is to provide clock pulses to the counter, for those pulses which peak
between the LOW DISC and HIGH DISC threshold levels. The LOW DISC threshold is adjusted with
potentiometer R3 and measured at TP2. The HIGH DISC threshold is adjusted with potentiometer R2 and
is measured at TP1. When the signal level goes above LOW DISC threshold, Z7 pin 6 will go low. The
first half of flip-flop Z19 clocks and then latch. When the signal goes below LOW DISC threshold, Z7 pin 6
return to a high state. This will provide a clock pulse into the second half flip-flop of Z19. Z19 pin 8 will
goes low and CLOCK is active (high). The clock is fed to the counter circuit.
If the signal level goes above the HIGH DISC threshold, Z7 pin 1 will go low. This will reset the first flip-
flop. When the signal goes below the LOW DISC threshold, the second flip-flop is clocked keeping Z19
pin 8 high. Therefore Z22 pin 8 is low inactive and this pulse is not counted.
2.4 Counters
The CLOCK pulse from Z22 is inverted by inverting Schmidt trigger Z21. Z21 provides a negative going
clock pulse for Z24. Z24, Z25, and Z26 are 16-bit dual module counters. Bits 1 through 8 are from Z24.
Z25 contains bits 9 through 16 and Z26 pins 3 and 4 are bits 17 and 18 respectively. Bit 18 is a stop bit
that causes the CLOCK to stay low and is also provided to register 3 to indicate overrange. The output of
the counters are input to registers 0, 1, and 3 and are available to the bus upon READ 0, READ 1, or
READ 3 control signals. Register 0, 1, and 3 are read only registers.