IBASE MI945 - Manual (Page 38)

BIOS SETUP
34 MI945 User’s Manual
Advanced Chipset Features
This Setup menu controls the configuration of the chipset.
Phoenix - AwardBIOS CMOS Setup Utility
Advanced Chipset Features
System BIOS Cacheable Enabled ITEM HELP
Memory Hole at 15M-16M Disabled
PCI Express Root Port Func Press Enter
** VGA Setting **
PEG/On Chip VGA Control Auto
PEG Force X1 Disabled
On-Chip Frame Buffer Size 32MB
DVMT Mode DVMT
DVMT/FIXED memory Size 128MB
Boot Display CRT+LVDS
SDVO Device Setting None
SDVO LVDS Protocol 1CH SPWG, 18bit
SDVO Panel Number 1024x768
Active LVDS Device No LVDS
Panel Scaling Auto
Panel Number 1024x768 18 bit SC
System BIOS Cacheable
The setting of Enabled allows caching of the system BIOS ROM at
F000h-FFFFFh, resulting in better system performance. However, if any
program writes to this memory area, a system error may result.
Memory Hole At 15M-16M
In order to improve performance, certain space in memory can be
reserved for ISA cards. This memory must be mapped into the memory
space below 16 MB. The choices are Enabled and Disabled.
Note: SDVO Device Setting, SDVO LVDS Protocol and SDVO Panel
Number Selection fields are available when ID390, ID390C, ID391,
ID391D or ID392 daughter cards are installed.